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Commit b26ff127 authored by Sergej Sawazki's avatar Sergej Sawazki Committed by Stephen Boyd
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clk: si5351: Apply PLL soft reset before enabling the outputs 

The "Si5351A/B/C Data Sheet" states to apply a PLL soft reset before
enabling the output clocks [1]. This is required to get a deterministic
phase relationship between the output clocks.

Without resetting the PLL, the phase relationship between the clocks is
unpredictable. Fix this by resetting the PLL in si5351_clkout_prepare().

References:
[1] https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf


    Figure 12 ("I2C Programming Procedure")

Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: default avatarSergej Sawazki <sergej@taudac.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 51279ef9

drivers/clk/clk-si5351.c

+29 −0
Original line number Original line Diff line number Diff line
@@ -903,13 +903,42 @@ static int _si5351_clkout_set_disable_state( 
	return 0;

	return 0;

}

}





void _si5351_clkout_reset_pll(struct si5351_driver_data *drvdata, int num)

{

	u8 val = si5351_reg_read(drvdata, SI5351_CLK0_CTRL + num);



	switch (val & SI5351_CLK_INPUT_MASK) {

	case SI5351_CLK_INPUT_XTAL:

	case SI5351_CLK_INPUT_CLKIN:

		return;  /* pll not used, no need to reset */

	}



	si5351_reg_write(drvdata, SI5351_PLL_RESET,

			 val & SI5351_CLK_PLL_SELECT ? SI5351_PLL_RESET_B :

						       SI5351_PLL_RESET_A);



	dev_dbg(&drvdata->client->dev, "%s - %s: pll = %d\n",

		__func__, clk_hw_get_name(&drvdata->clkout[num].hw),

		(val & SI5351_CLK_PLL_SELECT) ? 1 : 0);

}



static int si5351_clkout_prepare(struct clk_hw *hw)

static int si5351_clkout_prepare(struct clk_hw *hw)

{

{

	struct si5351_hw_data *hwdata =

	struct si5351_hw_data *hwdata =

		container_of(hw, struct si5351_hw_data, hw);

		container_of(hw, struct si5351_hw_data, hw);

	struct si5351_platform_data *pdata =

		hwdata->drvdata->client->dev.platform_data;





	si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,

	si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,

			SI5351_CLK_POWERDOWN, 0);

			SI5351_CLK_POWERDOWN, 0);



	/*

	 * Do a pll soft reset on the parent pll -- needed to get a

	 * deterministic phase relationship between the output clocks.

	 */

	if (pdata->clkout[hwdata->num].pll_reset)

		_si5351_clkout_reset_pll(hwdata->drvdata, hwdata->num);



	si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,

	si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,

			(1 << hwdata->num), 0);

			(1 << hwdata->num), 0);

	return 0;

	return 0;