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Commit b26a6fea authored by Peng Li's avatar Peng Li Committed by David S. Miller
Browse files

net: hns3: Enable HW GRO for Rev B(=0x21) HNS3 hardware 



HNS3 hardware Revision B(=0x21) supports Hardware GRO feature. This
patch enables this feature in the HNS3 PF/VF driver.

Signed-off-by: default avatarPeng Li <lipeng321@huawei.com>
Signed-off-by: default avatarSalil Mehta <salil.mehta@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ba2f55b0

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+4 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
#define HNAE3_UNIC_CLIENT_INITED_B		0x4

#define HNAE3_ROCE_CLIENT_INITED_B		0x5

#define HNAE3_DEV_SUPPORT_FD_B			0x6

#define HNAE3_DEV_SUPPORT_GRO_B			0x7



#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\

		BIT(HNAE3_DEV_SUPPORT_ROCE_B))
@@ -65,6 +66,9 @@ 
#define hnae3_dev_fd_supported(hdev) \

	hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B)



#define hnae3_dev_gro_supported(hdev) \

	hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B)



#define ring_ptr_move_fw(ring, p) \

	((ring)->p = ((ring)->p + 1) % (ring)->desc_num)

#define ring_ptr_move_bw(ring, p) \

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+3 −1
Original line number Diff line number Diff line
@@ -1714,8 +1714,10 @@ static void hns3_disable_sriov(struct pci_dev *pdev) 
static void hns3_get_dev_capability(struct pci_dev *pdev,

				    struct hnae3_ae_dev *ae_dev)

{

	if (pdev->revision >= 0x21)

	if (pdev->revision >= 0x21) {

		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);

		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);

	}

}



/* hns3_probe - Device initialization routine

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+7 −0
Original line number Diff line number Diff line
@@ -152,6 +152,7 @@ enum hclge_opcode_type { 


	/* TSO command */

	HCLGE_OPC_TSO_GENERIC_CONFIG	= 0x0C01,

	HCLGE_OPC_GRO_GENERIC_CONFIG    = 0x0C10,



	/* RSS commands */

	HCLGE_OPC_RSS_GENERIC_CONFIG	= 0x0D01,
@@ -758,6 +759,12 @@ struct hclge_cfg_tso_status_cmd { 
	u8 rsv[20];

};



#define HCLGE_GRO_EN_B		0

struct hclge_cfg_gro_status_cmd {

	__le16 gro_en;

	u8 rsv[22];

};



#define HCLGE_TSO_MSS_MIN	256

#define HCLGE_TSO_MSS_MAX	9668

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+30 −0
Original line number Diff line number Diff line
@@ -921,6 +921,28 @@ static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min, 
	return hclge_cmd_send(&hdev->hw, &desc, 1);

}



static int hclge_config_gro(struct hclge_dev *hdev, bool en)

{

	struct hclge_cfg_gro_status_cmd *req;

	struct hclge_desc desc;

	int ret;



	if (!hnae3_dev_gro_supported(hdev))

		return 0;



	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false);

	req = (struct hclge_cfg_gro_status_cmd *)desc.data;



	req->gro_en = cpu_to_le16(en ? 1 : 0);



	ret = hclge_cmd_send(&hdev->hw, &desc, 1);

	if (ret)

		dev_err(&hdev->pdev->dev,

			"GRO hardware config cmd failed, ret = %d\n", ret);



	return ret;

}



static int hclge_alloc_tqps(struct hclge_dev *hdev)

{

	struct hclge_tqp *tqp;
@@ -7090,6 +7112,10 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 
		goto err_mdiobus_unreg;

	}



	ret = hclge_config_gro(hdev, true);

	if (ret)

		goto err_mdiobus_unreg;



	ret = hclge_init_vlan_config(hdev);

	if (ret) {

		dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
@@ -7221,6 +7247,10 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 
		return ret;

	}



	ret = hclge_config_gro(hdev, true);

	if (ret)

		return ret;



	ret = hclge_init_vlan_config(hdev);

	if (ret) {

		dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h

+8 −0
Original line number Diff line number Diff line
@@ -87,6 +87,8 @@ enum hclgevf_opcode_type { 
	HCLGEVF_OPC_QUERY_TX_STATUS	= 0x0B03,

	HCLGEVF_OPC_QUERY_RX_STATUS	= 0x0B13,

	HCLGEVF_OPC_CFG_COM_TQP_QUEUE	= 0x0B20,

	/* GRO command */

	HCLGEVF_OPC_GRO_GENERIC_CONFIG  = 0x0C10,

	/* RSS cmd */

	HCLGEVF_OPC_RSS_GENERIC_CONFIG	= 0x0D01,

	HCLGEVF_OPC_RSS_INPUT_TUPLE     = 0x0D02,
@@ -149,6 +151,12 @@ struct hclgevf_query_res_cmd { 
	__le16 rsv[7];

};



#define HCLGEVF_GRO_EN_B               0

struct hclgevf_cfg_gro_status_cmd {

	__le16 gro_en;

	u8 rsv[22];

};



#define HCLGEVF_RSS_DEFAULT_OUTPORT_B	4

#define HCLGEVF_RSS_HASH_KEY_OFFSET_B	4

#define HCLGEVF_RSS_HASH_KEY_NUM	16