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Commit b22ca995 authored by Shashank Sharma's avatar Shashank Sharma Committed by Daniel Vetter
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drm/i915: prepare pipe for YCBCR420 output 



To get HDMI YCBCR420 output, the PIPEMISC register should be
programmed to:
- Generate YCBCR output (bit 11)
- In case of YCBCR420 outputs, it should be programmed in full
  blend mode to use the scaler in 5x3 ratio (bits 26 and 27)

This patch:
- Adds definition of these bits.
- Programs PIPEMISC for YCBCR420 outputs.
- Adds readouts to compare HW and SW states.

V2: rebase
V3: rebase
V4: rebase
V5: added r-b from Ander
V6: Handle only YCBCR420 outputs (ville)
V7: rebase
V8: Addressed review comments from Ville
    - Add readouts for state->ycbcr420 and 420 pixel_clock.
    - Handle warning due to mismatch in clock for ycbcr420 clock.
    - Rename PIPEMISC macros to match the Bspec.
    - Add a debug print stating if YCBCR 4:2:0 output enabled.
    Added r-b from Ville
V9: Addressed review comments from Imre:
    - Add 420 mode clock adjustment in intel_hdmi_mode_valid to
      prevent 420_only modes getting rejected for high clock.
    - Add port clock adjustment for ycbcr420 modes in ddi_get_clock
    - Rename macros as per Ville's suggestion.
    - Remove unnecessary wl changes.
V10: Added r-b from Imre
V11: Fixed faulty dotclock handling, and addressed missing comment
     from previous set of review comments (Imre)
V12: Fixed dotclock for 12bpc too, removed 420 check for GEN < 10

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Imre Deak <imre.deak@intel.com>

Reviewed-by: default avatarAnder Conselvan de Oliveira <conselvan2@gmail.com>
Reviewed-by: default avatarVille Syrjala <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarShashank Sharma <shashank.sharma@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1500904172-31717-1-git-send-email-shashank.sharma@intel.com


Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent e5c05931

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -5252,6 +5252,9 @@ enum { 


#define _PIPE_MISC_A			0x70030

#define _PIPE_MISC_B			0x71030

#define   PIPEMISC_YUV420_ENABLE	(1<<27)

#define   PIPEMISC_YUV420_MODE_FULL_BLEND (1<<26)

#define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1<<11)

#define   PIPEMISC_DITHER_BPC_MASK	(7<<5)

#define   PIPEMISC_DITHER_8_BPC		(0<<5)

#define   PIPEMISC_DITHER_10_BPC	(1<<5)

drivers/gpu/drm/i915/intel_ddi.c

+3 −0
Original line number Diff line number Diff line
@@ -1174,6 +1174,9 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 
	else

		dotclock = pipe_config->port_clock;



	if (pipe_config->ycbcr420)

		dotclock *= 2;



	if (pipe_config->pixel_multiplier)

		dotclock /= pipe_config->pixel_multiplier;

drivers/gpu/drm/i915/intel_display.c

+27 −0
Original line number Diff line number Diff line
@@ -7933,6 +7933,7 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc) 
{

	struct drm_i915_private *dev_priv = to_i915(crtc->dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct intel_crtc_state *config = intel_crtc->config;



	if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {

		u32 val = 0;
@@ -7958,6 +7959,12 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc) 
		if (intel_crtc->config->dither)

			val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;



		if (config->ycbcr420) {

			val |= PIPEMISC_OUTPUT_COLORSPACE_YUV |

				PIPEMISC_YUV420_ENABLE |

				PIPEMISC_YUV420_MODE_FULL_BLEND;

		}



		I915_WRITE(PIPEMISC(intel_crtc->pipe), val);

	}

}
@@ -9022,6 +9029,23 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, 
	pipe_config->gamma_mode =

		I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;



	if (IS_BROADWELL(dev_priv) || dev_priv->info.gen >= 9) {

		u32 tmp = I915_READ(PIPEMISC(crtc->pipe));

		bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV;



		if (IS_GEMINILAKE(dev_priv) || dev_priv->info.gen >= 10) {

			bool blend_mode_420 = tmp &

					      PIPEMISC_YUV420_MODE_FULL_BLEND;



			pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE;

			if (pipe_config->ycbcr420 != clrspace_yuv ||

			    pipe_config->ycbcr420 != blend_mode_420)

				DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp);

		} else if (clrspace_yuv) {

			DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n");

		}

	}



	power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);

	if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {

		power_domain_mask |= BIT_ULL(power_domain);
@@ -10401,6 +10425,9 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, 
				      pipe_config->fdi_lanes,

				      &pipe_config->fdi_m_n);



	if (pipe_config->ycbcr420)

		DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n");



	if (intel_crtc_has_dp_encoder(pipe_config)) {

		intel_dump_m_n_config(pipe_config, "dp m_n",

				pipe_config->lane_count, &pipe_config->dp_m_n);

drivers/gpu/drm/i915/intel_hdmi.c

+3 −0
Original line number Diff line number Diff line
@@ -1295,6 +1295,9 @@ intel_hdmi_mode_valid(struct drm_connector *connector, 
	if (mode->flags & DRM_MODE_FLAG_DBLCLK)

		clock *= 2;



	if (drm_mode_is_420_only(&connector->display_info, mode))

		clock /= 2;



	/* check if we can do 8bpc */

	status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);