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Commit b1d6f155 authored Dec 03, 2018 by Ingo Molnar Committed by Arnaldo Carvalho de Melo Dec 17, 2018

perf vendor events intel: Fix diverse typos



Go over the tools/ files that are maintained in Arnaldo's tree and
fix common typos: half of them were in comments, the other half
in JSON files.

( Care should be taken not to re-import these typos in the future,
  if the JSON files get updated by the vendor without fixing the typos. )

No change in functionality intended.

Committer notes:

This was split from a larger patch as there are code that is,
additionally, maintained outside the kernel tree, so to ease cherry
picking and/or backporting, split this into multiple patches.

Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20181203102200.GA104797@gmail.com


Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

parent 24f96733

tools/perf/pmu-events/arch/x86/broadwell/cache.json

+2 −2

Original line number	Diff line number	Diff line
		@@ -433,7 +433,7 @@
		},
		{
		"PEBS": "1",
		"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
		"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
		"EventCode": "0xD0",
		"Counter": "0,1,2,3",
		"UMask": "0x41",
		@@ -445,7 +445,7 @@
		},
		{
		"PEBS": "1",
		"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
		"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
		"EventCode": "0xD0",
		"Counter": "0,1,2,3",
		"UMask": "0x42",

tools/perf/pmu-events/arch/x86/broadwell/pipeline.json

+1 −1

Original line number	Diff line number	Diff line
		@@ -317,7 +317,7 @@
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},
		{
		"PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
		"PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
		"EventCode": "0x87",
		"Counter": "0,1,2,3",
		"UMask": "0x1",

tools/perf/pmu-events/arch/x86/broadwellde/cache.json

+2 −2

Original line number	Diff line number	Diff line
		@@ -439,7 +439,7 @@
		"PEBS": "1",
		"Counter": "0,1,2,3",
		"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
		"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
		"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -451,7 +451,7 @@
		"PEBS": "1",
		"Counter": "0,1,2,3",
		"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
		"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
		"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
		"SampleAfterValue": "100003",
		"L1_Hit_Indication": "1",
		"CounterHTOff": "0,1,2,3"

tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json

+1 −1

Original line number	Diff line number	Diff line
		@@ -322,7 +322,7 @@
		"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
		"Counter": "0,1,2,3",
		"EventName": "ILD_STALL.LCP",
		"PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
		"PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
		"SampleAfterValue": "2000003",
		"CounterHTOff": "0,1,2,3,4,5,6,7"
		},

tools/perf/pmu-events/arch/x86/broadwellx/cache.json

+2 −2

Original line number	Diff line number	Diff line
		@@ -439,7 +439,7 @@
		"PEBS": "1",
		"Counter": "0,1,2,3",
		"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
		"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
		"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
		"SampleAfterValue": "100003",
		"CounterHTOff": "0,1,2,3"
		},
		@@ -451,7 +451,7 @@
		"PEBS": "1",
		"Counter": "0,1,2,3",
		"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
		"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
		"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
		"SampleAfterValue": "100003",
		"L1_Hit_Indication": "1",
		"CounterHTOff": "0,1,2,3"