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Commit b1c4f7fe authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2019-04-17' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



UAPI Changes:

- uAPI "Fixes:" patch for the upcoming kernel 5.1, included here too

  We have an Ack from the media folks (only current user) for this
  late tweak

Cross-subsystem Changes:

- ALSA: hda: Fix racy display power access (Takashi, Chris)

Driver Changes:

- DDI and MIPI-DSI clocks fixes for Icelake (Vandita)
- Fix Icelake frequency change/locking (RPS) (Mika)
- Temporarily disable ppGTT read-only bit on Icelake (Mika)
- Add missing Icelake W/As (Mika)
- Enable 12 deep CSB status FIFO on Icelake (Mika)
- Inherit more Icelake code for Elkhartlake (Bob, Jani)

- Handle catastrophic error on engine reset (Mika)
- Shortcut readiness to reset check (Mika)
- Regression fix for GEM_BUSY causing us to report a mixed uabi-class request as not busy (Chris)
- Revert back to max link rate and lane count on eDP (Jani)
- Fix pipe BPP readout for BXT/GLK DSI (Ville)
- Set DP min_bpp to 8*3 for non-RGB output formats (Ville)
- Enable coarse preemption boundaries for Gen8 (Chris)
- Do not enable FEC without DSC (Ville)
- Restore correct BXT DDI latency optim setting calculation (Ville)
- Always reset context's RING registers to avoid running workload twice during reset (Chris)
- Set GPU wedged on driver unload (Janusz)
- Consolidate two similar barries from timeline into one (Chris)
- Only reset the pinned kernel contexts on resume (Chris)
- Wakeref tracking improvements (Chris, Imre)
- Lockdep fixes for shrinker interactions (Chris)
- Bump ready tasks ahead of busywaits in prep of semaphore use (Chris)

- Huge step in splitting display code into fine grained files (Jani)
- Refactor the IRQ init/reset macros for code saving (Paulo)
- Convert IRQ initialization code to uncore MMIO access (Paulo)
- Convert workarounds code to use uncore MMIO access (Chris)
- Nuke drm_crtc_state and use intel_atomic_state instead (Manasi)
- Update SKL clock-gating WA (Radhakrishna, Ville)
- Isolate GuC reset code flow (Chris)
- Expose force_dsc_enable through debugfs (Manasi)
- Header standalone compile testing framework (Jani)
- Code cleanups to reduce driver footprint (Chris)
- PSR code fixes and cleanups (Jose)
- Sparse and kerneldoc updates (Chris)
- Suppress spurious combo PHY B warning (Vile)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190418080426.GA6409@jlahtine-desk.ger.corp.intel.com
parents b3edf499 ad2c467a

arch/x86/kernel/early-quirks.c

+3 −1
Original line number Diff line number Diff line
@@ -525,7 +525,8 @@ static const struct pci_device_id intel_early_ids[] __initconst = { 
	INTEL_I945G_IDS(&gen3_early_ops),

	INTEL_I945GM_IDS(&gen3_early_ops),

	INTEL_VLV_IDS(&gen6_early_ops),

	INTEL_PINEVIEW_IDS(&gen3_early_ops),

	INTEL_PINEVIEW_G_IDS(&gen3_early_ops),

	INTEL_PINEVIEW_M_IDS(&gen3_early_ops),

	INTEL_I965G_IDS(&gen3_early_ops),

	INTEL_G33_IDS(&gen3_early_ops),

	INTEL_I965GM_IDS(&gen3_early_ops),
@@ -547,6 +548,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { 
	INTEL_GLK_IDS(&gen9_early_ops),

	INTEL_CNL_IDS(&gen9_early_ops),

	INTEL_ICL_11_IDS(&gen11_early_ops),

	INTEL_EHL_IDS(&gen11_early_ops),

};



struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);

drivers/gpu/drm/i915/.gitignore

0 → 100644
+1 −0
Original line number Diff line number Diff line 
header_test_*.c

drivers/gpu/drm/i915/Makefile

+4 −10
Original line number Diff line number Diff line
@@ -32,10 +32,13 @@ CFLAGS_intel_fbdev.o = $(call cc-disable-warning, override-init) 
subdir-ccflags-y += \

	$(call as-instr,movntdqa (%eax)$(comma)%xmm0,-DCONFIG_AS_MOVNTDQA)



# Extra header tests

include $(src)/Makefile.header-test



# Please keep these build lists sorted!



# core driver code

i915-y := i915_drv.o \

i915-y += i915_drv.o \

	  i915_irq.o \

	  i915_memcpy.o \

	  i915_mm.o \
@@ -57,15 +60,6 @@ i915-$(CONFIG_COMPAT) += i915_ioc32.o 
i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o

i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o



# Test the headers are compilable as standalone units

i915-$(CONFIG_DRM_I915_WERROR) += \

	test_i915_active_types_standalone.o \

	test_i915_gem_context_types_standalone.o \

	test_i915_timeline_types_standalone.o \

	test_intel_context_types_standalone.o \

	test_intel_engine_types_standalone.o \

	test_intel_workarounds_types_standalone.o



# GEM code

i915-y += \

	  i915_active.o \

drivers/gpu/drm/i915/Makefile.header-test

0 → 100644
+47 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: MIT

# Copyright © 2019 Intel Corporation



# Test the headers are compilable as standalone units

header_test := \

	i915_active_types.h \

	i915_gem_context_types.h \

	i915_priolist_types.h \

	i915_scheduler_types.h \

	i915_timeline_types.h \

	intel_atomic_plane.h \

	intel_audio.h \

	intel_cdclk.h \

	intel_color.h \

	intel_connector.h \

	intel_context_types.h \

	intel_crt.h \

	intel_csr.h \

	intel_ddi.h \

	intel_dp.h \

	intel_dvo.h \

	intel_engine_types.h \

	intel_fbc.h \

	intel_fbdev.h \

	intel_frontbuffer.h \

	intel_hdcp.h \

	intel_hdmi.h \

	intel_lspcon.h \

	intel_lvds.h \

	intel_panel.h \

	intel_pipe_crc.h \

	intel_pm.h \

	intel_psr.h \

	intel_sdvo.h \

	intel_sprite.h \

	intel_tv.h \

	intel_workarounds_types.h



quiet_cmd_header_test = HDRTEST $@

      cmd_header_test = echo "\#include \"$(<F)\"" > $@



header_test_%.c: %.h

	$(call cmd,header_test)



i915-$(CONFIG_DRM_I915_WERROR) += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.o,$(h)))



clean-files += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.c,$(h)))

drivers/gpu/drm/i915/gvt/cmd_parser.c

+28 −2
Original line number Diff line number Diff line
@@ -1077,6 +1077,7 @@ static int cmd_handler_pipe_control(struct parser_exec_state *s) 
	bool index_mode = false;

	unsigned int post_sync;

	int ret = 0;

	u32 hws_pga, val;



	post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
@@ -1100,6 +1101,15 @@ static int cmd_handler_pipe_control(struct parser_exec_state *s) 
					index_mode = true;

				ret |= cmd_address_audit(s, gma, sizeof(u64),

						index_mode);

				if (ret)

					return ret;

				if (index_mode) {

					hws_pga = s->vgpu->hws_pga[s->ring_id];

					gma = hws_pga + gma;

					patch_value(s, cmd_ptr(s, 2), gma);

					val = cmd_val(s, 1) & (~(1 << 21));

					patch_value(s, cmd_ptr(s, 1), val);

				}

			}

		}

	}
@@ -1317,8 +1327,14 @@ static int gen8_update_plane_mmio_from_mi_display_flip( 
			      info->tile_val << 10);

	}



	vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;

	if (info->plane == PLANE_PRIMARY)

		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++;



	if (info->async_flip)

		intel_vgpu_trigger_virtual_event(vgpu, info->event);

	else

		set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);



	return 0;

}
@@ -1563,6 +1579,7 @@ static int cmd_handler_mi_flush_dw(struct parser_exec_state *s) 
	unsigned long gma;

	bool index_mode = false;

	int ret = 0;

	u32 hws_pga, val;



	/* Check post-sync and ppgtt bit */

	if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
@@ -1573,6 +1590,15 @@ static int cmd_handler_mi_flush_dw(struct parser_exec_state *s) 
		if (cmd_val(s, 0) & (1 << 21))

			index_mode = true;

		ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);

		if (ret)

			return ret;

		if (index_mode) {

			hws_pga = s->vgpu->hws_pga[s->ring_id];

			gma = hws_pga + gma;

			patch_value(s, cmd_ptr(s, 1), gma);

			val = cmd_val(s, 0) & (~(1 << 21));

			patch_value(s, cmd_ptr(s, 0), val);

		}

	}

	/* Check notify bit */

	if ((cmd_val(s, 0) & (1 << 8)))