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Commit b1b80349 authored by Eugen Hristev's avatar Eugen Hristev Committed by Greg Kroah-Hartman
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mmc: sdhci-of-at91: fix set_uhs_signaling rewriting of MC1R 



[ Upstream commit 5987e6ded29d52e42fc7b06aa575c60a25eee38e ]

In set_uhs_signaling, the DDR bit is being set by fully writing the MC1R
register.
This can lead to accidental erase of certain bits in this register.
Avoid this by doing a read-modify-write operation.

Fixes: d0918764 ("mmc: sdhci-of-at91: fix MMC_DDR_52 timing selection")
Signed-off-by: default avatarEugen Hristev <eugen.hristev@microchip.com>
Tested-by: default avatarKarl Olsen <karl@micro-technic.com>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20220630090926.15061-1-eugen.hristev@microchip.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 9d8b911f

drivers/mmc/host/sdhci-of-at91.c

+7 −2
Original line number Diff line number Diff line
@@ -109,8 +109,13 @@ static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode, 
static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,

					 unsigned int timing)

{

	if (timing == MMC_TIMING_MMC_DDR52)

		sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);

	u8 mc1r;



	if (timing == MMC_TIMING_MMC_DDR52) {

		mc1r = sdhci_readb(host, SDMMC_MC1R);

		mc1r |= SDMMC_MC1R_DDR;

		sdhci_writeb(host, mc1r, SDMMC_MC1R);

	}

	sdhci_set_uhs_signaling(host, timing);

}