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Commit b14fc502 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/8xx: regroup TLB handler routines 



As this is running with MMU off, the CPU only does speculative
fetch for code in the same page.

Following the significant size reduction of TLB handler routines,
the side handlers can be brought back close to the main part,
ie in the same page.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 74fabcad

arch/powerpc/kernel/head_8xx.S

+54 −58
Original line number Diff line number Diff line
@@ -399,6 +399,23 @@ InstructionTLBMiss: 
	rfi

#endif



#ifndef CONFIG_PIN_TLB_TEXT

ITLBMissLinear:

	mtcr	r11

	/* Set 8M byte page and mark it valid */

	li	r11, MI_PS8MEG | MI_SVALID

	mtspr	SPRN_MI_TWC, r11

	rlwinm	r10, r10, 20, 0x0f800000	/* 8xx supports max 256Mb RAM */

	ori	r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \

			  _PAGE_PRESENT

	mtspr	SPRN_MI_RPN, r10	/* Update TLB entry */



0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

	rfi

	patch_site	0b, patch__itlbmiss_exit_2

#endif



	. = 0x1200

DataStoreTLBMiss:

	mtspr	SPRN_SPRG_SCRATCH0, r10
@@ -484,6 +501,43 @@ DataStoreTLBMiss: 
	rfi

#endif



DTLBMissIMMR:

	mtcr	r11

	/* Set 512k byte guarded page and mark it valid */

	li	r10, MD_PS512K | MD_GUARDED | MD_SVALID

	mtspr	SPRN_MD_TWC, r10

	mfspr	r10, SPRN_IMMR			/* Get current IMMR */

	rlwinm	r10, r10, 0, 0xfff80000		/* Get 512 kbytes boundary */

	ori	r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \

			  _PAGE_PRESENT | _PAGE_NO_CACHE

	mtspr	SPRN_MD_RPN, r10	/* Update TLB entry */



	li	r11, RPN_PATTERN

	mtspr	SPRN_DAR, r11	/* Tag DAR */



0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

	rfi

	patch_site	0b, patch__dtlbmiss_exit_2



DTLBMissLinear:

	mtcr	r11

	/* Set 8M byte page and mark it valid */

	li	r11, MD_PS8MEG | MD_SVALID

	mtspr	SPRN_MD_TWC, r11

	rlwinm	r10, r10, 20, 0x0f800000	/* 8xx supports max 256Mb RAM */

	ori	r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \

			  _PAGE_PRESENT

	mtspr	SPRN_MD_RPN, r10	/* Update TLB entry */



	li	r11, RPN_PATTERN

	mtspr	SPRN_DAR, r11	/* Tag DAR */



0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

	rfi

	patch_site	0b, patch__dtlbmiss_exit_3



/* This is an instruction TLB error on the MPC8xx.  This could be due

 * to many reasons, such as executing guarded memory or illegal instruction

 * addresses.  There is nothing to do but handle a big time error fault.
@@ -583,64 +637,6 @@ InstructionBreakpoint: 


	. = 0x2000



/*

 * Bottom part of DataStoreTLBMiss handlers for IMMR area and linear RAM.

 * not enough space in the DataStoreTLBMiss area.

 */

DTLBMissIMMR:

	mtcr	r11

	/* Set 512k byte guarded page and mark it valid */

	li	r10, MD_PS512K | MD_GUARDED | MD_SVALID

	mtspr	SPRN_MD_TWC, r10

	mfspr	r10, SPRN_IMMR			/* Get current IMMR */

	rlwinm	r10, r10, 0, 0xfff80000		/* Get 512 kbytes boundary */

	ori	r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \

			  _PAGE_PRESENT | _PAGE_NO_CACHE

	mtspr	SPRN_MD_RPN, r10	/* Update TLB entry */



	li	r11, RPN_PATTERN

	mtspr	SPRN_DAR, r11	/* Tag DAR */



0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

	rfi

	patch_site	0b, patch__dtlbmiss_exit_2



DTLBMissLinear:

	mtcr	r11

	/* Set 8M byte page and mark it valid */

	li	r11, MD_PS8MEG | MD_SVALID

	mtspr	SPRN_MD_TWC, r11

	rlwinm	r10, r10, 20, 0x0f800000	/* 8xx supports max 256Mb RAM */

	ori	r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \

			  _PAGE_PRESENT

	mtspr	SPRN_MD_RPN, r10	/* Update TLB entry */



	li	r11, RPN_PATTERN

	mtspr	SPRN_DAR, r11	/* Tag DAR */



0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

	rfi

	patch_site	0b, patch__dtlbmiss_exit_3



#ifndef CONFIG_PIN_TLB_TEXT

ITLBMissLinear:

	mtcr	r11

	/* Set 8M byte page and mark it valid */

	li	r11, MI_PS8MEG | MI_SVALID

	mtspr	SPRN_MI_TWC, r11

	rlwinm	r10, r10, 20, 0x0f800000	/* 8xx supports max 256Mb RAM */

	ori	r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \

			  _PAGE_PRESENT

	mtspr	SPRN_MI_RPN, r10	/* Update TLB entry */



0:	mfspr	r10, SPRN_SPRG_SCRATCH0

	mfspr	r11, SPRN_SPRG_SCRATCH1

	rfi

	patch_site	0b, patch__itlbmiss_exit_2

#endif



/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions

 * by decoding the registers used by the dcbx instruction and adding them.

 * DAR is set to the calculated address.