clk: qcom: Add support for VIDEOCC clock driver for YUPIK (b113aa18) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/clk/qcom/Kconfig

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		@@ -647,4 +647,13 @@ config SC_DEBUGCC_SHRIKE
		Say Y if you want to support the debug clocks such as
		clock measurement functionality.

		config SM_VIDEOCC_YUPIK
		tristate "YUPIK Video Clock Controller"
		select SM_GCC_YUPIK
		help
		Support for the video clock controller on Qualcomm Technologies, Inc.
		YUPIK devices.
		Say Y if you want to support video devices and functionality such as
		video encode/decode.

		endif

drivers/clk/qcom/Makefile

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		@@ -91,6 +91,7 @@ obj-$(CONFIG_SM_NPUCC_8150) += npucc-sm8150.o
		obj-$(CONFIG_SM_SCC_8150) += scc-sm8150.o
		obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
		obj-$(CONFIG_SM_VIDEOCC_SHIMA) += videocc-shima.o
		obj-$(CONFIG_SM_VIDEOCC_YUPIK) += videocc-yupik.o
		obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
		obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
		obj-$(CONFIG_QCOM_HFPLL) += hfpll.o

drivers/clk/qcom/videocc-yupik.c

0 → 100644

+433 −0

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		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2020, The Linux Foundation. All rights reserved.
		*/

		#include <linux/clk-provider.h>
		#include <linux/kernel.h>
		#include <linux/module.h>
		#include <linux/of_device.h>
		#include <linux/of.h>
		#include <linux/pm_clock.h>
		#include <linux/pm_runtime.h>
		#include <linux/regmap.h>

		#include <dt-bindings/clock/qcom,videocc-yupik.h>

		#include "clk-alpha-pll.h"
		#include "clk-branch.h"
		#include "clk-rcg.h"
		#include "common.h"
		#include "reset.h"
		#include "vdd-level.h"

		static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH + 1, 1, vdd_corner);

		static struct clk_vdd_class *video_cc_yupik_regulators[] = {
		&vdd_cx,
		};

		enum {
		P_BI_TCXO,
		P_SLEEP_CLK,
		P_VIDEO_PLL0_OUT_EVEN,
		};

		static struct pll_vco lucid_vco[] = {
		{ 249600000, 2000000000, 0 },
		};

		/* 400MHz Configuration */
		static const struct alpha_pll_config video_pll0_config = {
		.l = 0x14,
		.alpha = 0xD555,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00002261,
		.config_ctl_hi1_val = 0x329A299C,
		.user_ctl_val = 0x00000001,
		.user_ctl_hi_val = 0x00000805,
		.user_ctl_hi1_val = 0x00000000,
		};

		static struct clk_alpha_pll video_pll0 = {
		.offset = 0x0,
		.vco_table = lucid_vco,
		.num_vco = ARRAY_SIZE(lucid_vco),
		.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
		.clkr = {
		.hw.init = &(struct clk_init_data){
		.name = "video_pll0",
		.parent_data = &(const struct clk_parent_data){
		.fw_name = "bi_tcxo",
		},
		.num_parents = 1,
		.ops = &clk_alpha_pll_lucid_ops,
		},
		.vdd_data = {
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 615000000,
		[VDD_LOW] = 1066000000,
		[VDD_LOW_L1] = 1600000000,
		[VDD_NOMINAL] = 2000000000},
		},
		},
		};

		static const struct parent_map video_cc_parent_map_0[] = {
		{ P_BI_TCXO, 0 },
		{ P_VIDEO_PLL0_OUT_EVEN, 3 },
		};

		static const struct clk_parent_data video_cc_parent_data_0[] = {
		{ .fw_name = "bi_tcxo" },
		{ .hw = &video_pll0.clkr.hw },
		};

		static const struct parent_map video_cc_parent_map_1[] = {
		{ P_SLEEP_CLK, 0 },
		};

		static const struct clk_parent_data video_cc_parent_data_1[] = {
		{ .fw_name = "sleep_clk" },
		};

		static const struct parent_map video_cc_parent_map_2[] = {
		{ P_BI_TCXO, 0 },
		};

		static const struct clk_parent_data video_cc_parent_data_2_ao[] = {
		{ .fw_name = "bi_tcxo_ao" },
		};

		static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
		F(133333333, P_VIDEO_PLL0_OUT_EVEN, 3, 0, 0),
		F(240000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
		F(335000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
		F(424000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
		F(460000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
		{ }
		};

		static struct clk_rcg2 video_cc_iris_clk_src = {
		.cmd_rcgr = 0x1000,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_0,
		.freq_tbl = ftbl_video_cc_iris_clk_src,
		.enable_safe_config = true,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "video_cc_iris_clk_src",
		.parent_data = video_cc_parent_data_0,
		.num_parents = ARRAY_SIZE(video_cc_parent_data_0),
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		},
		.clkr.vdd_data = {
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_LOWER] = 133333333,
		[VDD_LOW] = 240000000,
		[VDD_LOW_L1] = 335000000,
		[VDD_NOMINAL] = 424000000,
		[VDD_HIGH] = 460000000},
		},
		};

		static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
		F(32000, P_SLEEP_CLK, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 video_cc_sleep_clk_src = {
		.cmd_rcgr = 0x701c,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_1,
		.freq_tbl = ftbl_video_cc_sleep_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "video_cc_sleep_clk_src",
		.parent_data = video_cc_parent_data_1,
		.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
		.ops = &clk_rcg2_ops,
		},
		.clkr.vdd_data = {
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_LOWER] = 32000},
		},
		};

		static const struct freq_tbl ftbl_video_cc_xo_clk_src[] = {
		F(19200000, P_BI_TCXO, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 video_cc_xo_clk_src = {
		.cmd_rcgr = 0x7000,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = video_cc_parent_map_2,
		.freq_tbl = ftbl_video_cc_xo_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "video_cc_xo_clk_src",
		.parent_data = video_cc_parent_data_2_ao,
		.num_parents = ARRAY_SIZE(video_cc_parent_data_2_ao),
		.ops = &clk_rcg2_ops,
		},
		};

		static struct clk_branch video_cc_iris_ahb_clk = {
		.halt_reg = 0x5004,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x5004,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_iris_ahb_clk",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_iris_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvs0_axi_clk = {
		.halt_reg = 0x800c,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x800c,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_mvs0_axi_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvs0_core_clk = {
		.halt_reg = 0x3010,
		.halt_check = BRANCH_HALT_VOTED,
		.hwcg_reg = 0x3010,
		.hwcg_bit = 1,
		.clkr = {
		.enable_reg = 0x3010,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_mvs0_core_clk",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_iris_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvsc_core_clk = {
		.halt_reg = 0x2014,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x2014,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_mvsc_core_clk",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_iris_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_mvsc_ctl_axi_clk = {
		.halt_reg = 0x8004,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x8004,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_mvsc_ctl_axi_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_sleep_clk = {
		.halt_reg = 0x7034,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x7034,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_sleep_clk",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_sleep_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_venus_ahb_clk = {
		.halt_reg = 0x801c,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x801c,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_venus_ahb_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch video_cc_xo_clk = {
		.halt_reg = 0x7018,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x7018,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "video_cc_xo_clk",
		.parent_data = &(const struct clk_parent_data){
		.hw = &video_cc_xo_clk_src.clkr.hw,
		},
		.num_parents = 1,
		.flags = CLK_IS_CRITICAL \| CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_regmap *video_cc_yupik_clocks[] = {
		[VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr,
		[VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr,
		[VIDEO_CC_MVS0_AXI_CLK] = &video_cc_mvs0_axi_clk.clkr,
		[VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr,
		[VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr,
		[VIDEO_CC_MVSC_CTL_AXI_CLK] = &video_cc_mvsc_ctl_axi_clk.clkr,
		[VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr,
		[VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
		[VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
		[VIDEO_CC_XO_CLK] = &video_cc_xo_clk.clkr,
		[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
		[VIDEO_PLL0] = &video_pll0.clkr,
		};

		static const struct qcom_reset_map video_cc_yupik_resets[] = {
		[VCODEC_VIDEO_CC_INTERFACE_AHB_BCR] = { 0x5000 },
		[VCODEC_VIDEO_CC_INTERFACE_BCR] = { 0x8000 },
		[VCODEC_VIDEO_CC_MVS0_BCR] = { 0x3000 },
		[VCODEC_VIDEO_CC_MVSC_BCR] = { 0x2000 },
		};

		static const struct regmap_config video_cc_yupik_regmap_config = {
		.reg_bits = 32,
		.reg_stride = 4,
		.val_bits = 32,
		.max_register = 0xb000,
		.fast_io = true,
		};

		static const struct qcom_cc_desc video_cc_yupik_desc = {
		.config = &video_cc_yupik_regmap_config,
		.clks = video_cc_yupik_clocks,
		.num_clks = ARRAY_SIZE(video_cc_yupik_clocks),
		.resets = video_cc_yupik_resets,
		.num_resets = ARRAY_SIZE(video_cc_yupik_resets),
		.clk_regulators = video_cc_yupik_regulators,
		.num_clk_regulators = ARRAY_SIZE(video_cc_yupik_regulators),
		};

		static const struct of_device_id video_cc_yupik_match_table[] = {
		{ .compatible = "qcom,yupik-videocc" },
		{ }
		};
		MODULE_DEVICE_TABLE(of, video_cc_yupik_match_table);

		static int video_cc_yupik_probe(struct platform_device *pdev)
		{
		struct regmap *regmap;
		int ret;

		regmap = qcom_cc_map(pdev, &video_cc_yupik_desc);
		if (IS_ERR(regmap))
		return PTR_ERR(regmap);

		pm_runtime_enable(&pdev->dev);
		ret = pm_clk_create(&pdev->dev);
		if (ret)
		goto disable_pm_runtime;

		ret = pm_clk_add(&pdev->dev, "cfg_ahb");
		if (ret < 0) {
		dev_err(&pdev->dev, "Unable to get ahb clock handle\n");
		goto destroy_pm_clk;
		}

		clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);

		ret = qcom_cc_really_probe(pdev, &video_cc_yupik_desc, regmap);
		if (ret) {
		dev_err(&pdev->dev, "Failed to register VIDEO CC clocks\n");
		goto destroy_pm_clk;
		}

		dev_info(&pdev->dev, "Registered VIDEO CC clocks\n");

		return 0;

		destroy_pm_clk:
		pm_clk_destroy(&pdev->dev);

		disable_pm_runtime:
		pm_runtime_disable(&pdev->dev);

		return ret;
		}

		static const struct dev_pm_ops video_cc_yupik_pm_ops = {
		SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
		};

		static void video_cc_yupik_sync_state(struct device *dev)
		{
		qcom_cc_sync_state(dev, &video_cc_yupik_desc);
		}

		static struct platform_driver video_cc_yupik_driver = {
		.probe = video_cc_yupik_probe,
		.driver = {
		.name = "video_cc-yupik",
		.of_match_table = video_cc_yupik_match_table,
		.sync_state = video_cc_yupik_sync_state,
		.pm = &video_cc_yupik_pm_ops,
		},
		};

		static int __init video_cc_yupik_init(void)
		{
		return platform_driver_register(&video_cc_yupik_driver);
		}
		subsys_initcall(video_cc_yupik_init);

		static void __exit video_cc_yupik_exit(void)
		{
		platform_driver_unregister(&video_cc_yupik_driver);
		}
		module_exit(video_cc_yupik_exit);

		MODULE_DESCRIPTION("QTI VIDEO_CC YUPIK Driver");
		MODULE_LICENSE("GPL v2");