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Commit b0c4c898 authored by Hartley Sweeten's avatar Hartley Sweeten Committed by Russell King
Browse files

ARM: 6025/1: vic: factor out common init code 



This factors out the common initialization code for the two vic
vendors into easier maintainable functions.

Tested-by: default avatarLinus Walleij <linus.walleij@stericsson.com>
Tested-by: default avatarAlessandro Rubini <rubini@unipv.it>
Cc: Andrea Gallo <andrea.gallo@stericsson.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 39710479

arch/arm/common/vic.c

+52 −55
Original line number Diff line number Diff line
@@ -273,6 +273,46 @@ static struct irq_chip vic_chip = { 
	.set_wake	= vic_set_wake,

};



static void __init vic_disable(void __iomem *base)

{

	writel(0, base + VIC_INT_SELECT);

	writel(0, base + VIC_INT_ENABLE);

	writel(~0, base + VIC_INT_ENABLE_CLEAR);

	writel(0, base + VIC_IRQ_STATUS);

	writel(0, base + VIC_ITCR);

	writel(~0, base + VIC_INT_SOFT_CLEAR);

}



static void __init vic_clear_interrupts(void __iomem *base)

{

	unsigned int i;



	writel(0, base + VIC_PL190_VECT_ADDR);

	for (i = 0; i < 19; i++) {

		unsigned int value;



		value = readl(base + VIC_PL190_VECT_ADDR);

		writel(value, base + VIC_PL190_VECT_ADDR);

	}

}



static void __init vic_set_irq_sources(void __iomem *base,

				unsigned int irq_start, u32 vic_sources)

{

	unsigned int i;



	for (i = 0; i < 32; i++) {

		if (vic_sources & (1 << i)) {

			unsigned int irq = irq_start + i;



			set_irq_chip(irq, &vic_chip);

			set_irq_chip_data(irq, base);

			set_irq_handler(irq, handle_level_irq);

			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);

		}

	}

}



/*

 * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.

 * The original cell has 32 interrupts, while the modified one has 64,
@@ -287,13 +327,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start, 
	int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;



	/* Disable all interrupts initially. */



	writel(0, base + VIC_INT_SELECT);

	writel(0, base + VIC_INT_ENABLE);

	writel(~0, base + VIC_INT_ENABLE_CLEAR);

	writel(0, base + VIC_IRQ_STATUS);

	writel(0, base + VIC_ITCR);

	writel(~0, base + VIC_INT_SOFT_CLEAR);

	vic_disable(base);



	/*

	 * Make sure we clear all existing interrupts. The vector registers
@@ -302,13 +336,8 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start, 
	 * the second base address, which is 0x20 in the page

	 */

	if (vic_2nd_block) {

		writel(0, base + VIC_PL190_VECT_ADDR);

		for (i = 0; i < 19; i++) {

			unsigned int value;

		vic_clear_interrupts(base);



			value = readl(base + VIC_PL190_VECT_ADDR);

			writel(value, base + VIC_PL190_VECT_ADDR);

		}

		/* ST has 16 vectors as well, but we don't enable them by now */

		for (i = 0; i < 16; i++) {

			void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
@@ -318,16 +347,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start, 
		writel(32, base + VIC_PL190_DEF_VECT_ADDR);

	}



	for (i = 0; i < 32; i++) {

		if (vic_sources & (1 << i)) {

			unsigned int irq = irq_start + i;



			set_irq_chip(irq, &vic_chip);

			set_irq_chip_data(irq, base);

			set_irq_handler(irq, handle_level_irq);

			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);

		}

	}

	vic_set_irq_sources(base, irq_start, vic_sources);

}



/**
@@ -365,37 +385,14 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, 
	}



	/* Disable all interrupts initially. */

	vic_disable(base);



	writel(0, base + VIC_INT_SELECT);

	writel(0, base + VIC_INT_ENABLE);

	writel(~0, base + VIC_INT_ENABLE_CLEAR);

	writel(0, base + VIC_IRQ_STATUS);

	writel(0, base + VIC_ITCR);

	writel(~0, base + VIC_INT_SOFT_CLEAR);



	/*

	 * Make sure we clear all existing interrupts

	 */

	writel(0, base + VIC_PL190_VECT_ADDR);

	for (i = 0; i < 19; i++) {

		unsigned int value;



		value = readl(base + VIC_PL190_VECT_ADDR);

		writel(value, base + VIC_PL190_VECT_ADDR);

	}

	/* Make sure we clear all existing interrupts */

	vic_clear_interrupts(base);



	vic_init2(base);



	for (i = 0; i < 32; i++) {

		if (vic_sources & (1 << i)) {

			unsigned int irq = irq_start + i;



			set_irq_chip(irq, &vic_chip);

			set_irq_chip_data(irq, base);

			set_irq_handler(irq, handle_level_irq);

			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);

		}

	}

	vic_set_irq_sources(base, irq_start, vic_sources);



	vic_pm_register(base, irq_start, resume_sources);

}