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Commit b0c351b5 authored by Philipp Zabel's avatar Philipp Zabel Committed by Mauro Carvalho Chehab
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media: dt-bindings: media: Add i.MX Pixel Pipeline binding



Add DT binding documentation for the Pixel Pipeline (PXP) found on
various NXP i.MX SoCs.

Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
parent 20b00bbe
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Freescale Pixel Pipeline
========================

The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
that supports scaling, colorspace conversion, alpha blending, rotation, and
pixel conversion via lookup table. Different versions are present on various
i.MX SoCs from i.MX23 to i.MX7.

Required properties:
- compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28,
  imx6dl, imx6sl, imx6ul, imx6sx, imx6ull, or imx7d.
- reg: the register base and size for the device registers
- interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d.
- clock-names: should be "axi"
- clocks: the PXP AXI clock

Example:

pxp@21cc000 {
	compatible = "fsl,imx6ull-pxp";
	reg = <0x021cc000 0x4000>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "axi";
	clocks = <&clks IMX6UL_CLK_PXP>;
};