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Commit afe4d089 authored by John Garry's avatar John Garry Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events arm64: fixup A53 to use recommended events 



This patch fixes the ARM Cortex-A53 json to use event definition from
the ARMv8 recommended events.

In addition to this change, other changes were made:

- remove stray ','
- remove mirrored events in memory.json and bus.json
- fixed indentation to be consistent with other ARM
  JSONs

Signed-off-by: default avatarJohn Garry <john.garry@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: http://lkml.kernel.org/r/1520506716-197429-11-git-send-email-john.garry@huawei.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent ae43053b

tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json

+6 −8
Original line number Diff line number Diff line 
[

  {,

    "EventCode": "0x7A",

    "EventName": "BR_INDIRECT_SPEC",

    "BriefDescription": "Branch speculatively executed - Indirect branch"

  {

    "ArchStdEvent":  "BR_INDIRECT_SPEC",

  },

  {,

  {

    "EventCode": "0xC9",

    "EventName": "BR_COND",

    "BriefDescription": "Conditional branch executed"

  },

  {,

  {

    "EventCode": "0xCA",

    "EventName": "BR_INDIRECT_MISPRED",

    "BriefDescription": "Indirect branch mispredicted"

  },

  {,

  {

    "EventCode": "0xCB",

    "EventName": "BR_INDIRECT_MISPRED_ADDR",

    "BriefDescription": "Indirect branch mispredicted because of address miscompare"

  },

  {,

  {

    "EventCode": "0xCC",

    "EventName": "BR_COND_MISPRED",

    "BriefDescription": "Conditional branch mispredicted"

tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json

+4 −18
Original line number Diff line number Diff line 
[

  {,

    "EventCode": "0x60",

    "EventName": "BUS_ACCESS_LD",

    "BriefDescription": "Bus access - Read"

  {

        "ArchStdEvent": "BUS_ACCESS_RD",

  },

  {,

    "EventCode": "0x61",

    "EventName": "BUS_ACCESS_ST",

    "BriefDescription": "Bus access - Write"

  },

  {,

    "EventCode": "0xC0",

    "EventName": "EXT_MEM_REQ",

    "BriefDescription": "External memory request"

  },

  {,

    "EventCode": "0xC1",

    "EventName": "EXT_MEM_REQ_NC",

    "BriefDescription": "Non-cacheable external memory request"

  {

        "ArchStdEvent": "BUS_ACCESS_WR",

  }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json

+20 −20
Original line number Diff line number Diff line 
[

  {,

  {

        "EventCode": "0xC2",

        "EventName": "PREFETCH_LINEFILL",

        "BriefDescription": "Linefill because of prefetch"

  },

  {,

  {

        "EventCode": "0xC3",

        "EventName": "PREFETCH_LINEFILL_DROP",

        "BriefDescription": "Instruction Cache Throttle occurred"

  },

  {,

  {

        "EventCode": "0xC4",

        "EventName": "READ_ALLOC_ENTER",

        "BriefDescription": "Entering read allocate mode"

  },

  {,

  {

        "EventCode": "0xC5",

        "EventName": "READ_ALLOC",

        "BriefDescription": "Read allocate mode"

  },

  {,

  {

        "EventCode": "0xC8",

        "EventName": "EXT_SNOOP",

        "BriefDescription": "SCU Snooped data from another CPU for this CPU"

tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json

+2 −12
Original line number Diff line number Diff line 
[

  {,

    "EventCode": "0x60",

    "EventName": "BUS_ACCESS_LD",

    "BriefDescription": "Bus access - Read"

  },

  {,

    "EventCode": "0x61",

    "EventName": "BUS_ACCESS_ST",

    "BriefDescription": "Bus access - Write"

  },

  {,

  {

    "EventCode": "0xC0",

    "EventName": "EXT_MEM_REQ",

    "BriefDescription": "External memory request"

  },

  {,

  {

    "EventCode": "0xC1",

    "EventName": "EXT_MEM_REQ_NC",

    "BriefDescription": "Non-cacheable external memory request"

tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json

+20 −24
Original line number Diff line number Diff line 
[

  {,

    "EventCode": "0x86",

    "EventName": "EXC_IRQ",

    "BriefDescription": "Exception taken, IRQ"

  {

        "ArchStdEvent": "EXC_IRQ",

  },

  {,

    "EventCode": "0x87",

    "EventName": "EXC_FIQ",

    "BriefDescription": "Exception taken, FIQ"

  {

        "ArchStdEvent": "EXC_FIQ",

  },

  {,

  {

        "EventCode": "0xC6",

        "EventName": "PRE_DECODE_ERR",

        "BriefDescription": "Pre-decode error"

  },

  {,

  {

        "EventCode": "0xD0",

        "EventName": "L1I_CACHE_ERR",

        "BriefDescription": "L1 Instruction Cache (data or tag) memory error"

  },

  {,

  {

        "EventCode": "0xD1",

        "EventName": "L1D_CACHE_ERR",

        "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"

  },

  {,

  {

        "EventCode": "0xD2",

        "EventName": "TLB_ERR",

        "BriefDescription": "TLB memory error"