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Commit afa957e5 authored by Mukund Madhusudan Atre's avatar Mukund Madhusudan Atre Committed by Gerrit - the friendly Code Review server
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msm: camera: isp: Write zero to clear register after global clear command



Clear registers hold the programmed values unless explicitly set to zero.
This can cause problems in cases where a global clear is issued which
encompasses the registers for which clear mask was set in a different
instance of IRQ controller. We should not wait for the next IRQ to clear
the undesired bits in clear register. This change makes sure that the
actions of a particular IRQ controller do not affect the other. Write
zeros explicitly to clear registers corresponding to status registers
after global clear is issued in IRQ handler.

CRs-Fixed: 2775499
Change-Id: Ic57302e5862d9453a94c4e8f470215dacb8978ec
Signed-off-by: default avatarMukund Madhusudan Atre <matre@codeaurora.org>
parent 6f7f5948
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+14 −5
Original line number Diff line number Diff line
@@ -722,6 +722,7 @@ irqreturn_t cam_irq_controller_handle_irq(int irq_num, void *priv)
			if (irq_register->top_half_enable_mask[j] &
				controller->irq_status_arr[i])
				need_th_processing[j] = true;

			CAM_DBG(CAM_IRQ_CTRL,
				"i %d j %d need_th_processing = %d",
				i, j, need_th_processing[j]);
@@ -730,11 +731,19 @@ irqreturn_t cam_irq_controller_handle_irq(int irq_num, void *priv)

	CAM_DBG(CAM_IRQ_CTRL, "Status Registers read Successful");

	if (controller->global_clear_offset)
	if (controller->global_clear_offset) {
		cam_io_w_mb(controller->global_clear_bitmask,
			controller->mem_base + controller->global_clear_offset);
		for (i = 0; i < controller->num_registers; i++) {
			irq_register = &controller->irq_register_arr[i];
			if (controller->irq_status_arr[i])
				cam_io_w_mb(0x0, controller->mem_base +
					irq_register->clear_reg_offset);
		}

	CAM_DBG(CAM_IRQ_CTRL, "Status Clear done");
		CAM_DBG(CAM_IRQ_CTRL, "Global Clear done from %s",
			controller->name);
	}

	for (i = 0; i < CAM_IRQ_PRIORITY_MAX; i++) {
		if (need_th_processing[i]) {