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Commit af0f0120 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "icnss2: Enable PHY processor SSR along with WPSS SSR"

parents 24557c6d 047f485e

arch/arm64/configs/vendor/lahaina_QGKI.config

+1 −0
Original line number Diff line number Diff line
@@ -168,6 +168,7 @@ CONFIG_SLIMBUS_MSM_NGD=m 
CONFIG_QCOM_KGSL=y

CONFIG_QCOM_KGSL_CONTEXT_DEBUG=y

CONFIG_QCOM_QFPROM=y

CONFIG_ICNSS2_RESTART_LEVEL_NOTIF=y

CONFIG_ARM_QCOM_CPUFREQ_HW=y

CONFIG_NETFILTER_XT_TARGET_TEE=y

CONFIG_NETFILTER_XT_TARGET_NOTRACK=y

drivers/soc/qcom/icnss2/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -28,6 +28,15 @@ config ICNSS2_QMI 
	  and configurations. It also send WLAN on/off control message to FW

	  over QMI channel.



config ICNSS2_RESTART_LEVEL_NOTIF

	bool "Enable Restart level change notification"

	depends on ICNSS2

	help

	  Say 'Y' here to enable ICNSS2_RESTART_LEVEL_NOTIF support.

	  This will be needed to register notifier and get notification for

	  restart_level change of WLAN Sub system. On receiving notification

	  ICNSS2 enable/disable M3 SSR. This is only enabled for QGKI config.



config CNSS_QCA6750

	bool "Enable ICNSS QCA6750 chipset specific changes"

	depends on ICNSS2

drivers/soc/qcom/icnss2/main.c

+23 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ 
#include <soc/qcom/ramdump.h>

#include <linux/soc/qcom/smem.h>

#include <linux/soc/qcom/smem_state.h>

#include <trace/events/trace_msm_ssr_event.h>

#include "main.h"

#include "qmi.h"

#include "debug.h"
@@ -3907,6 +3908,22 @@ static inline bool icnss_use_nv_mac(struct icnss_priv *priv) 
				     "use-nv-mac");

}



#ifdef CONFIG_ICNSS2_RESTART_LEVEL_NOTIF

static void pil_restart_level_notifier(void *ignore,

			      int restart_level,

			      const char *fw)

{

	icnss_pr_err("PIL Notifier, restart_level: %d, FW:%s",

		     restart_level, fw);

	if (!strcmp(fw, "wpss")) {

		if (restart_level == RESET_SUBSYS_COUPLED)

			icnss_send_smp2p(penv, ICNSS_ENABLE_M3_SSR);

		else

			icnss_send_smp2p(penv, ICNSS_DISABLE_M3_SSR);

	}

}

#endif



static int icnss_probe(struct platform_device *pdev)

{

	int ret = 0;
@@ -4023,6 +4040,9 @@ static int icnss_probe(struct platform_device *pdev) 
		icnss_pr_dbg("NV MAC feature is %s\n",

			     priv->use_nv_mac ? "Mandatory":"Not Mandatory");

		INIT_WORK(&wpss_loader, icnss_wpss_load);

#ifdef CONFIG_ICNSS2_RESTART_LEVEL_NOTIF

		register_trace_pil_restart_level(pil_restart_level_notifier, NULL);

#endif

	}



	INIT_LIST_HEAD(&priv->icnss_tcdev_list);
@@ -4054,6 +4074,9 @@ static int icnss_remove(struct platform_device *pdev) 
		icnss_dms_deinit(priv);

		icnss_genl_exit();

		icnss_runtime_pm_deinit(priv);

#ifdef CONFIG_ICNSS2_RESTART_LEVEL_NOTIF

		unregister_trace_pil_restart_level(pil_restart_level_notifier, NULL);

#endif

	}



	device_init_wakeup(&priv->pdev->dev, false);

drivers/soc/qcom/icnss2/main.h

+4 −0
Original line number Diff line number Diff line
@@ -183,6 +183,10 @@ enum icnss_smp2p_msg_id { 
	ICNSS_POWER_SAVE_ENTER = 1,

	ICNSS_POWER_SAVE_EXIT,

	ICNSS_TRIGGER_SSR,

#ifdef CONFIG_ICNSS2_RESTART_LEVEL_NOTIF

	ICNSS_ENABLE_M3_SSR,

	ICNSS_DISABLE_M3_SSR,

#endif

	ICNSS_PCI_EP_POWER_SAVE_ENTER = 6,

	ICNSS_PCI_EP_POWER_SAVE_EXIT,

};