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Commit aeb18dd0 authored by Jose Abreu's avatar Jose Abreu Committed by David S. Miller
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net: stmmac: xgmac: Disable MMC interrupts by default 



MMC interrupts were being enabled, which is not what we want because it
will lead to a storm of interrupts that are not handled at all. Fix it
by disabling all MMC interrupts for XGMAC.

Fixes: b6cdf09f ("net: stmmac: xgmac: Implement MMC counters")
Signed-off-by: default avatarJose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 132f2f20

drivers/net/ethernet/stmicro/stmmac/mmc_core.c

+4 −2
Original line number Diff line number Diff line
@@ -176,6 +176,7 @@ 
#define MMC_XGMAC_RX_PKT_SMD_ERR	0x22c

#define MMC_XGMAC_RX_PKT_ASSEMBLY_OK	0x230

#define MMC_XGMAC_RX_FPE_FRAG		0x234

#define MMC_XGMAC_RX_IPC_INTR_MASK	0x25c



static void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)

{
@@ -333,8 +334,9 @@ static void dwxgmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode) 


static void dwxgmac_mmc_intr_all_mask(void __iomem *mmcaddr)

{

	writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_INTR_MASK);

	writel(MMC_DEFAULT_MASK, mmcaddr + MMC_TX_INTR_MASK);

	writel(0x0, mmcaddr + MMC_RX_INTR_MASK);

	writel(0x0, mmcaddr + MMC_TX_INTR_MASK);

	writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_IPC_INTR_MASK);

}



static void dwxgmac_read_mmc_reg(void __iomem *addr, u32 reg, u32 *dest)