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Commit aea71020 authored by Douglas Anderson's avatar Douglas Anderson Committed by Amit Pundir
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UPSTREAM: ath10k: Get rid of "per_ce_irq" hw param 



[ Upstream commit 7f86551665121931ecd6d327e019e7a69782bfcd ]

As of the patch ("ath10k: Keep track of which interrupts fired, don't
poll them") we now have no users of this hardware parameter.  Remove
it.

Suggested-by: default avatarBrian Norris <briannorris@chromium.org>
Signed-off-by: default avatarDouglas Anderson <dianders@chromium.org>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20200709082024.v2.2.I083faa4e62e69f863311c89ae5eb28ec5a229b70@changeid


Stable-dep-of: 170c75d43a77 ("ath10k: Don't touch the CE interrupt registers after power up")
Signed-off-by: default avatarAmit Pundir <amit.pundir@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Bug: 146449535
Change-Id: I221d9cc30d009c3bc87a7943f8e3da1931984e1e
Signed-off-by: default avatarAmit Pundir <amit.pundir@linaro.org>
(cherry picked from android11-5.4-lts commit c2d9b438)
parent 89945968

drivers/net/wireless/ath/ath10k/core.c

+0 −13
Original line number Diff line number Diff line
@@ -118,7 +118,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_wds_entries = 0x20,

		.target_64bit = false,

		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,

		.per_ce_irq = false,

		.shadow_reg_support = false,

		.rri_on_ddr = false,

		.hw_filter_reset_required = true,
@@ -154,7 +153,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_wds_entries = 0x20,

		.target_64bit = false,

		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,

		.per_ce_irq = false,

		.shadow_reg_support = false,

		.rri_on_ddr = false,

		.hw_filter_reset_required = true,
@@ -217,7 +215,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_wds_entries = 0x20,

		.target_64bit = false,

		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,

		.per_ce_irq = false,

		.shadow_reg_support = false,

		.rri_on_ddr = false,

		.hw_filter_reset_required = true,
@@ -252,7 +249,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_wds_entries = 0x20,

		.target_64bit = false,

		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,

		.per_ce_irq = false,

		.shadow_reg_support = false,

		.rri_on_ddr = false,

		.hw_filter_reset_required = true,
@@ -287,7 +283,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_wds_entries = 0x20,

		.target_64bit = false,

		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,

		.per_ce_irq = false,

		.shadow_reg_support = false,

		.rri_on_ddr = false,

		.hw_filter_reset_required = true,
@@ -325,7 +320,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_wds_entries = 0x20,

		.target_64bit = false,

		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,

		.per_ce_irq = false,

		.shadow_reg_support = false,

		.rri_on_ddr = false,

		.hw_filter_reset_required = true,
@@ -366,7 +360,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_wds_entries = 0x20,

		.target_64bit = false,

		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,

		.per_ce_irq = false,

		.shadow_reg_support = false,

		.rri_on_ddr = false,

		.hw_filter_reset_required = true,
@@ -414,7 +407,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_wds_entries = 0x20,

		.target_64bit = false,

		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,

		.per_ce_irq = false,

		.shadow_reg_support = false,

		.rri_on_ddr = false,

		.hw_filter_reset_required = true,
@@ -459,7 +451,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_wds_entries = 0x20,

		.target_64bit = false,

		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,

		.per_ce_irq = false,

		.shadow_reg_support = false,

		.rri_on_ddr = false,

		.hw_filter_reset_required = true,
@@ -494,7 +485,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_wds_entries = 0x20,

		.target_64bit = false,

		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,

		.per_ce_irq = false,

		.shadow_reg_support = false,

		.rri_on_ddr = false,

		.hw_filter_reset_required = true,
@@ -531,7 +521,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_wds_entries = 0x20,

		.target_64bit = false,

		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,

		.per_ce_irq = false,

		.shadow_reg_support = false,

		.rri_on_ddr = false,

		.hw_filter_reset_required = true,
@@ -573,7 +562,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_wds_entries = 0x20,

		.target_64bit = false,

		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,

		.per_ce_irq = false,

		.shadow_reg_support = false,

		.rri_on_ddr = false,

		.hw_filter_reset_required = true,
@@ -601,7 +589,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES,

		.target_64bit = true,

		.rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC,

		.per_ce_irq = true,

		.shadow_reg_support = true,

		.rri_on_ddr = true,

		.hw_filter_reset_required = false,

drivers/net/wireless/ath/ath10k/hw.h

+0 −3
Original line number Diff line number Diff line
@@ -590,9 +590,6 @@ struct ath10k_hw_params { 
	/* Target rx ring fill level */

	u32 rx_ring_fill_level;



	/* target supporting per ce IRQ */

	bool per_ce_irq;



	/* target supporting shadow register for ce write */

	bool shadow_reg_support;