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Commit adfbb80d authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v5.3-rockchip-dts32-2' of... 

Merge tag 'v5.3-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

Display support for rk3228/rk3229 (up to hdmi output) and more love
for rk3288-veyron boards.

* tag 'v5.3-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip

:
  ARM: dts: rockchip: add display nodes for rk322x
  ARM: dts: rockchip: fix vop iommu-cells on rk322x
  clk: rockchip: add clock id for hdmi_phy special clock on rk3228
  clk: rockchip: add clock id for watchdog pclk on rk3328
  Revert "ARM: dts: rockchip: set PWM delay backlight settings for Minnie"
  ARM: dts: rockchip: Configure BT_DEV_WAKE in on rk3288-veyron
  ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up signal on veyron

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 299a0458 519574e3

arch/arm/boot/dts/rk322x.dtsi

+84 −1
Original line number Diff line number Diff line
@@ -143,6 +143,11 @@ 
		#clock-cells = <0>;

	};



	display_subsystem: display-subsystem {

		compatible = "rockchip,display-subsystem";

		ports = <&vop_out>;

	};



	i2s1: i2s1@100b0000 {

		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";

		reg = <0x100b0000 0x4000>;
@@ -529,6 +534,17 @@ 
		status = "disabled";

	};



	hdmi_phy: hdmi-phy@12030000 {

		compatible = "rockchip,rk3228-hdmi-phy";

		reg = <0x12030000 0x10000>;

		clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;

		clock-names = "sysclk", "refoclk", "refpclk";

		#clock-cells = <0>;

		clock-output-names = "hdmiphy_phy";

		#phy-cells = <0>;

		status = "disabled";

	};



	gpu: gpu@20000000 {

		compatible = "rockchip,rk3228-mali", "arm,mali-400";

		reg = <0x20000000 0x10000>;
@@ -572,6 +588,28 @@ 
		status = "disabled";

	};



	vop: vop@20050000 {

		compatible = "rockchip,rk3228-vop";

		reg = <0x20050000 0x1ffc>;

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;

		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";

		resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;

		reset-names = "axi", "ahb", "dclk";

		iommus = <&vop_mmu>;

		status = "disabled";



		vop_out: port {

			#address-cells = <1>;

			#size-cells = <0>;



			vop_out_hdmi: endpoint@0 {

				reg = <0>;

				remote-endpoint = <&hdmi_in_vop>;

			};

		};

	};



	vop_mmu: iommu@20053f00 {

		compatible = "rockchip,iommu";

		reg = <0x20053f00 0x100>;
@@ -579,7 +617,7 @@ 
		interrupt-names = "vop_mmu";

		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;

		clock-names = "aclk", "iface";

		iommu-cells = <0>;

		#iommu-cells = <0>;

		status = "disabled";

	};
@@ -594,6 +632,36 @@ 
		status = "disabled";

	};



	hdmi: hdmi@200a0000 {

		compatible = "rockchip,rk3228-dw-hdmi";

		reg = <0x200a0000 0x20000>;

		reg-io-width = <4>;

		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

		assigned-clocks = <&cru SCLK_HDMI_PHY>;

		assigned-clock-parents = <&hdmi_phy>;

		clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;

		clock-names = "isfr", "iahb", "cec";

		pinctrl-names = "default";

		pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;

		resets = <&cru SRST_HDMI_P>;

		reset-names = "hdmi";

		phys = <&hdmi_phy>;

		phy-names = "hdmi";

		rockchip,grf = <&grf>;

		status = "disabled";



		ports {

			hdmi_in: port {

				#address-cells = <1>;

				#size-cells = <0>;

				hdmi_in_vop: endpoint@0 {

					reg = <0>;

					remote-endpoint = <&vop_out_hdmi>;

				};

			};

		};

	};



	sdmmc: dwmmc@30000000 {

		compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";

		reg = <0x30000000 0x4000>;
@@ -922,6 +990,21 @@ 
			};

		};



		hdmi {

			hdmi_hpd: hdmi-hpd {

				rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;

			};



			hdmii2c_xfer: hdmii2c-xfer {

				rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,

						<0 RK_PA7 2 &pcfg_pull_none>;

			};



			hdmi_cec: hdmi-cec {

				rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;

			};

		};



		i2c0 {

			i2c0_xfer: i2c0-xfer {

				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,

arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -237,6 +237,7 @@ 


		/* Wake only */

		&suspend_l_wake

		&bt_dev_wake_awake

	>;

	pinctrl-1 = <

		/* Common for sleep and wake, but no owners */
@@ -246,6 +247,7 @@ 


		/* Sleep only */

		&suspend_l_sleep

		&bt_dev_wake_sleep

	>;



	backlight {

arch/arm/boot/dts/rk3288-veyron-minnie.dts

+0 −2
Original line number Diff line number Diff line
@@ -106,8 +106,6 @@ 
			240 241 242 243 244 245 246 247

			248 249 250 251 252 253 254 255>;

	power-supply = <&backlight_regulator>;

	post-pwm-on-delay-ms = <200>;

	pwm-off-delay-ms = <200>;

};



&i2c_tunnel {

arch/arm/boot/dts/rk3288-veyron.dtsi

+49 −0
Original line number Diff line number Diff line
@@ -23,6 +23,31 @@ 
		reg = <0x0 0x0 0x0 0x80000000>;

	};



	bt_activity: bt-activity {

		compatible = "gpio-keys";

		pinctrl-names = "default";

		pinctrl-0 = <&bt_host_wake>;



		/*

		 * HACK: until we have an LPM driver, we'll use an

		 * ugly GPIO key to allow Bluetooth to wake from S3.

		 * This is expected to only be used by BT modules that

		 * use UART for comms.  For BT modules that talk over

		 * SDIO we should use a wakeup mechanism related to SDIO.

		 *

		 * Use KEY_RESERVED here since that will work as a wakeup but

		 * doesn't get reported to higher levels (so doesn't confuse

		 * Chrome).

		 */

		bt-wake {

			label = "BT Wakeup";

			gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;

			linux,code = <KEY_RESERVED>;

			wakeup-source;

		};



	};



	power_button: power-button {

		compatible = "gpio-keys";

		pinctrl-names = "default";
@@ -460,12 +485,18 @@ 
		&ddr0_retention

		&ddrio_pwroff

		&global_pwroff



		/* Wake only */

		&bt_dev_wake_awake

	>;

	pinctrl-1 = <

		/* Common for sleep and wake, but no owners */

		&ddr0_retention

		&ddrio_pwroff

		&global_pwroff



		/* Sleep only */

		&bt_dev_wake_sleep

	>;



	pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
@@ -549,6 +580,10 @@ 
			rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;

		};



		bt_host_wake: bt-host-wake {

			rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>;

		};



		/*

		 * We run sdio0 at max speed; bump up drive strength.

		 * We also have external pulls, so disable the internal ones.
@@ -567,6 +602,20 @@ 
		sdio0_clk: sdio0-clk {

			rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;

		};



		/*

		 * These pins are only present on very new veyron boards; on

		 * older boards bt_dev_wake is simply always high.  Note that

		 * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt

		 * to map this pin everywhere

		 */

		bt_dev_wake_sleep: bt-dev-wake-sleep {

			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>;

		};



		bt_dev_wake_awake: bt-dev-wake-awake {

			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;

		};

	};



	tpm {

include/dt-bindings/clock/rk3228-cru.h

+1 −0
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ 
#define SCLK_WIFI		141

#define SCLK_OTGPHY0		142

#define SCLK_OTGPHY1		143

#define SCLK_HDMI_PHY		144



/* dclk gates */

#define DCLK_VOP		190