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Commit ad830e7a authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: add vbios table check for enabling dp ss 



Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarEric Bernstein <Eric.Bernstein@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3e27e10e

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+1 −0
Original line number Diff line number Diff line
@@ -1038,6 +1038,7 @@ static bool construct( 
	link->link_index = init_params->link_index;



	link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);

	link->dp_ss_off = !!dc_ctx->dc_bios->integrated_info->dp_ss_control;;



	if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {

		dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+4 −1
Original line number Diff line number Diff line
@@ -953,6 +953,9 @@ enum link_training_result dc_link_dp_perform_link_training( 
	 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :

	 * LINK_SPREAD_DISABLED;

	 */

	if (link->dp_ss_off)

		lt_settings.link_settings.link_spread = LINK_SPREAD_DISABLED;

	else

		lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;



	/* 1. set link rate, lane count and spread*/

drivers/gpu/drm/amd/display/dc/dc_link.h

+1 −0
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ struct dc_link { 
	enum dc_irq_source irq_source_hpd;

	enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */

	bool is_hpd_filter_disabled;

	bool dp_ss_off;



	/* caps is the same as reported_link_cap. link_traing use

	 * reported_link_cap. Will clean up.  TODO

drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h

+2 −0
Original line number Diff line number Diff line
@@ -395,6 +395,8 @@ struct integrated_info { 
	struct i2c_reg_info dp3_ext_hdmi_reg_settings[9];

	unsigned char dp3_ext_hdmi_6g_reg_num;

	struct i2c_reg_info dp3_ext_hdmi_6g_reg_settings[3];

	/* V11 */

	uint32_t dp_ss_control;

};



/**