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Commit ad75174f authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-soc-5.1' of... 

Merge tag 'imx-soc-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX SoC changes for 5.1:
 - Support cpuidle for i.MX7ULP, states WFI, WAIT and STOP get added.
 - Support SoC revision detecting for i.MX7ULP by reading JTAG_ID
   register from SIM module.
 - Select PM and GPCv2 irqchip driver options for i.MX8 support, as they
   are essential for building an i.MX8 based system.
 - Skip build of ssi-fiq code if SND_SOC_IMX_PCM_FIQ is not enabled.

* tag 'imx-soc-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux

:
  arm64: imx8mq: select PM support
  arm64: imx8mq: select GPCv2 irqchip driver
  ARM: imx: add i.MX7ULP SoC revision support
  ARM: imx: add i.MX7ULP cpuidle support
  ARM: imx: don't build ssi-fiq if not required

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents e62538ff 84a2ab25

arch/arm/mach-imx/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -29,9 +29,10 @@ obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o 
obj-$(CONFIG_SOC_IMX6SLL) += cpuidle-imx6sx.o

obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o

obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6sx.o

obj-$(CONFIG_SOC_IMX7ULP) += cpuidle-imx7ulp.o

endif



ifdef CONFIG_SND_IMX_SOC

ifdef CONFIG_SND_SOC_IMX_PCM_FIQ

obj-y += ssi-fiq.o

obj-y += ssi-fiq-ksym.o

endif

arch/arm/mach-imx/common.h

+10 −0
Original line number Diff line number Diff line
@@ -72,6 +72,15 @@ enum mxc_cpu_pwr_mode { 
	STOP_POWER_OFF,		/* STOP + SRPG */

};



enum ulp_cpu_pwr_mode {

	ULP_PM_HSRUN,    /* High speed run mode */

	ULP_PM_RUN,      /* Run mode */

	ULP_PM_WAIT,     /* Wait mode */

	ULP_PM_STOP,     /* Stop mode */

	ULP_PM_VLPS,     /* Very low power stop mode */

	ULP_PM_VLLS,     /* very low leakage stop mode */

};



void imx_enable_cpu(int cpu, bool enable);

void imx_set_cpu_jump(int cpu, void *jump_addr);

u32 imx_get_cpu_arg(int cpu);
@@ -98,6 +107,7 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode); 
void imx6_set_int_mem_clk_lpm(bool enable);

void imx6sl_set_wait_clk(bool enter);

int imx_mmdc_get_ddr_type(void);

int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);



void imx_cpu_die(unsigned int cpu);

int imx_cpu_kill(unsigned int cpu);

arch/arm/mach-imx/cpuidle-imx7ulp.c

0 → 100644
+60 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright (C) 2016 Freescale Semiconductor, Inc.

 * Copyright 2017-2018 NXP

 *   Anson Huang <Anson.Huang@nxp.com>

 */



#include <linux/cpuidle.h>

#include <linux/module.h>

#include <asm/cpuidle.h>



#include "common.h"

#include "cpuidle.h"



static int imx7ulp_enter_wait(struct cpuidle_device *dev,

			    struct cpuidle_driver *drv, int index)

{

	if (index == 1)

		imx7ulp_set_lpm(ULP_PM_WAIT);

	else

		imx7ulp_set_lpm(ULP_PM_STOP);



	cpu_do_idle();



	imx7ulp_set_lpm(ULP_PM_RUN);



	return index;

}



static struct cpuidle_driver imx7ulp_cpuidle_driver = {

	.name = "imx7ulp_cpuidle",

	.owner = THIS_MODULE,

	.states = {

		/* WFI */

		ARM_CPUIDLE_WFI_STATE,

		/* WAIT */

		{

			.exit_latency = 50,

			.target_residency = 75,

			.enter = imx7ulp_enter_wait,

			.name = "WAIT",

			.desc = "PSTOP2",

		},

		/* STOP */

		{

			.exit_latency = 100,

			.target_residency = 150,

			.enter = imx7ulp_enter_wait,

			.name = "STOP",

			.desc = "PSTOP1",

		},

	},

	.state_count = 3,

	.safe_state_index = 0,

};



int __init imx7ulp_cpuidle_init(void)

{

	return cpuidle_register(&imx7ulp_cpuidle_driver, NULL);

}

arch/arm/mach-imx/cpuidle.h

+5 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ extern int imx5_cpuidle_init(void); 
extern int imx6q_cpuidle_init(void);

extern int imx6sl_cpuidle_init(void);

extern int imx6sx_cpuidle_init(void);

extern int imx7ulp_cpuidle_init(void);

#else

static inline int imx5_cpuidle_init(void)

{
@@ -32,4 +33,8 @@ static inline int imx6sx_cpuidle_init(void) 
{

	return 0;

}

static inline int imx7ulp_cpuidle_init(void)

{

	return 0;

}

#endif

arch/arm/mach-imx/mach-imx7ulp.c

+46 −0
Original line number Diff line number Diff line
@@ -6,17 +6,57 @@ 
 */



#include <linux/irqchip.h>

#include <linux/mfd/syscon.h>

#include <linux/of_platform.h>

#include <linux/regmap.h>

#include <asm/mach/arch.h>



#include "common.h"

#include "cpuidle.h"

#include "hardware.h"



#define SIM_JTAG_ID_REG		0x8c



static void __init imx7ulp_set_revision(void)

{

	struct regmap *sim;

	u32 revision;



	sim = syscon_regmap_lookup_by_compatible("fsl,imx7ulp-sim");

	if (IS_ERR(sim)) {

		pr_warn("failed to find fsl,imx7ulp-sim regmap!\n");

		return;

	}



	if (regmap_read(sim, SIM_JTAG_ID_REG, &revision)) {

		pr_warn("failed to read sim regmap!\n");

		return;

	}



	/*

	 * bit[31:28] of JTAG_ID register defines revision as below from B0:

	 * 0001        B0

	 * 0010        B1

	 */

	switch (revision >> 28) {

	case 1:

		imx_set_soc_revision(IMX_CHIP_REVISION_2_0);

		break;

	case 2:

		imx_set_soc_revision(IMX_CHIP_REVISION_2_1);

		break;

	default:

		imx_set_soc_revision(IMX_CHIP_REVISION_1_0);

		break;

	}

}



static void __init imx7ulp_init_machine(void)

{

	imx7ulp_pm_init();



	mxc_set_cpu_type(MXC_CPU_IMX7ULP);

	imx7ulp_set_revision();

	of_platform_default_populate(NULL, NULL, imx_soc_device_init());

}
@@ -25,7 +65,13 @@ static const char *const imx7ulp_dt_compat[] __initconst = { 
	NULL,

};



static void __init imx7ulp_init_late(void)

{

	imx7ulp_cpuidle_init();

}



DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")

	.init_machine	= imx7ulp_init_machine,

	.dt_compat	= imx7ulp_dt_compat,

	.init_late	= imx7ulp_init_late,

MACHINE_END