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Commit ad689220 authored by Thomas Gleixner's avatar Thomas Gleixner Committed by Ingo Molnar
Browse files

perf_counter, x86: Implement generalized cache event types, add Atom support 



Fill in core2_hw_cache_event_id[] with the Atom model specific events.

The events can be used in all the tools via the -e (--event) parameter,
for example "-e l1-misses" or -"-e l2-accesses" or "-e l2-write-misses".

( Note: these are straight from the Intel manuals - not tested yet.)

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 0312af84

arch/x86/kernel/cpu/perf_counter.c

+84 −1
Original line number Original line Diff line number Diff line
@@ -285,7 +285,90 @@ static const u64 atom_hw_cache_event_ids 
				[PERF_COUNT_HW_CACHE_OP_MAX]

				[PERF_COUNT_HW_CACHE_OP_MAX]

				[PERF_COUNT_HW_CACHE_RESULT_MAX] =

				[PERF_COUNT_HW_CACHE_RESULT_MAX] =

{

{

	/* To be filled in */

 [ C(L1D) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */

		[ C(RESULT_MISS)   ] = 0,

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = 0x2241, /* L1D_CACHE.ST               */

		[ C(RESULT_MISS)   ] = 0,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = 0x0,

		[ C(RESULT_MISS)   ] = 0,

	},

 },

 [ C(L1I ) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */

		[ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

 },

 [ C(L2  ) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */

		[ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */

		[ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

 },

 [ C(DTLB) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */

		[ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */

		[ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

	},

 },

 [ C(ITLB) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */

		[ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

	},

 },

 [ C(BPU ) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */

		[ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

	},

 },

};

};





static u64 intel_pmu_raw_event(u64 event)

static u64 intel_pmu_raw_event(u64 event)