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Commit acf86310 authored by Prudhvi Yarlagadda's avatar Prudhvi Yarlagadda
Browse files

serial: msm_geni_serial: Ensure to set clock freq correctly 



This patch enables UART clock to run at half the rate and make
sure write to register gets executed with read back of the same
regiter.

Change-Id: Ic4087f6e246b112769335e883a35d8eb00412907
Signed-off-by: default avatarPrudhvi Yarlagadda <pyarlaga@codeaurora.org>
parent 36dde607

drivers/tty/serial/msm_geni_serial.c

+12 −0
Original line number Diff line number Diff line
@@ -1992,6 +1992,10 @@ static void msm_geni_serial_set_termios(struct uart_port *uport, 
	unsigned long clk_rate;

	unsigned long flags;



	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);

	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);

	geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);



	if (!uart_console(uport)) {

		int ret = msm_geni_serial_power_on(uport);
@@ -2330,6 +2334,10 @@ msm_geni_serial_earlycon_setup(struct earlycon_device *dev, 
	 */

	msm_geni_serial_poll_cancel_tx(uport);



	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);

	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);

	geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);



	se_get_packing_config(8, 1, false, &cfg0, &cfg1);

	geni_se_init(uport->membase, (DEF_FIFO_DEPTH_WORDS >> 1),

					(DEF_FIFO_DEPTH_WORDS - 2));
@@ -2774,6 +2782,10 @@ static int msm_geni_serial_probe(struct platform_device *pdev) 
		pm_runtime_enable(&pdev->dev);

	}



	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);

	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);

	geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);



	dev_info(&pdev->dev, "Serial port%d added.FifoSize %d is_console%d\n",

				line, uport->fifosize, is_console);

	device_create_file(uport->dev, &dev_attr_loopback);