Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ac8320c4 authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Lee Jones
Browse files

mfd: twl6040: Correct HPPLL configuration for 19.2 and 38.4 MHz mclk 



When the MCLK is 19.2 or 38.4 MHz the HPPLL need to be enabled and can be
put in bypass mode.
This will fix HPPLL use on boards with 19.2MHz mclk.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
parent a58cc84c

drivers/mfd/twl6040.c

+5 −8
Original line number Diff line number Diff line
@@ -441,12 +441,9 @@ int twl6040_set_pll(struct twl6040 *twl6040, int pll_id, 
					    TWL6040_HPLLENA;

				break;

			case 19200000:

				/*

				* PLL disabled

				* (enable PLL if MCLK jitter quality

				*  doesn't meet specification)

				*/

				hppllctl |= TWL6040_MCLK_19200KHZ;

				/* PLL enabled, bypass mode */

				hppllctl |= TWL6040_MCLK_19200KHZ |

					    TWL6040_HPLLBP | TWL6040_HPLLENA;

				break;

			case 26000000:

				/* PLL enabled, active mode */
@@ -454,9 +451,9 @@ int twl6040_set_pll(struct twl6040 *twl6040, int pll_id, 
					    TWL6040_HPLLENA;

				break;

			case 38400000:

				/* PLL enabled, active mode */

				/* PLL enabled, bypass mode */

				hppllctl |= TWL6040_MCLK_38400KHZ |

					    TWL6040_HPLLENA;

					    TWL6040_HPLLBP | TWL6040_HPLLENA;

				break;

			default:

				dev_err(twl6040->dev,