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Commit ac56d484 authored by Isaac J. Manjarres's avatar Isaac J. Manjarres
Browse files

ARM: dts: msm: Update iommu-fault model values with new values 

Update the existing iommu-fault model values to maintain
the same behavior as before HUPCF and stall-disable were
split up for all targets.

Change-Id: Id28bc54e6c6c8db622927f6a34c5bb556222c1f5
parent 34588620

qcom/lahaina.dtsi

+21 −21
Original line number Diff line number Diff line
@@ -3356,7 +3356,7 @@ 
			iommus = <&apps_smmu 0x2161 0x0400>,

					 <&apps_smmu 0x1181 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3366,7 +3366,7 @@ 
			iommus = <&apps_smmu 0x2162 0x0400>,

					 <&apps_smmu 0x1182 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3376,7 +3376,7 @@ 
			iommus = <&apps_smmu 0x2163 0x0400>,

					 <&apps_smmu 0x1183 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3386,7 +3386,7 @@ 
			iommus = <&apps_smmu 0x2164 0x0400>,

					 <&apps_smmu 0x1184 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3396,7 +3396,7 @@ 
			iommus = <&apps_smmu 0x2165 0x0400>,

					 <&apps_smmu 0x1185 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3406,7 +3406,7 @@ 
			iommus = <&apps_smmu 0x2166 0x0400>,

					 <&apps_smmu 0x1186 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3416,7 +3416,7 @@ 
			iommus = <&apps_smmu 0x2167 0x0400>,

					 <&apps_smmu 0x1187 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3426,7 +3426,7 @@ 
			iommus = <&apps_smmu 0x2168 0x0400>,

					 <&apps_smmu 0x1188 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3437,7 +3437,7 @@ 
			iommus = <&apps_smmu 0x2169 0x0400>,

					 <&apps_smmu 0x1189 0x0420>;

			qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			qcom,iommu-vmid = <0xA>;	/* VMID_CP_PIXEL */

			dma-coherent-hint-cached;

		};
@@ -3447,7 +3447,7 @@ 
			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x1803 0x0>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3456,7 +3456,7 @@ 
			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x1804 0x0>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3465,7 +3465,7 @@ 
			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x1805 0x0>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3474,7 +3474,7 @@ 
			label = "sdsprpc-smd";

			iommus = <&apps_smmu 0x0541 0x0>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3483,7 +3483,7 @@ 
			label = "sdsprpc-smd";

			iommus = <&apps_smmu 0x0542 0x0>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3492,7 +3492,7 @@ 
			label = "sdsprpc-smd";

			iommus = <&apps_smmu 0x0543 0x0>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			shared-cb = <4>;

			dma-coherent-hint-cached;

		};
@@ -3503,7 +3503,7 @@ 
			iommus = <&apps_smmu 0x118B 0x0420>,

					 <&apps_smmu 0x216B 0x0400>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3513,7 +3513,7 @@ 
			iommus = <&apps_smmu 0x118C 0x0420>,

					 <&apps_smmu 0x216C 0x0400>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3523,7 +3523,7 @@ 
			iommus = <&apps_smmu 0x118D 0x0420>,

					 <&apps_smmu 0x216D 0x0400>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};
@@ -3533,7 +3533,7 @@ 
			iommus = <&apps_smmu 0x118E 0x0420>,

					 <&apps_smmu 0x216E 0x0400>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent-hint-cached;

		};

	};
@@ -5443,7 +5443,7 @@ 
			qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;

			qcom,iommu-dma = "fastmap";

			qcom,iommu-pagetable = "coherent";

			qcom,iommu-faults = "stall-disable", "no-CFRE",

			qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",

					    "non-fatal";

		};

	};

qcom/shima.dtsi

+16 −16
Original line number Diff line number Diff line
@@ -1366,7 +1366,7 @@ 
			iommus = <&apps_smmu 0x2961 0x0400>,

					 <&apps_smmu 0x1981 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent;

		};
@@ -1376,7 +1376,7 @@ 
			iommus = <&apps_smmu 0x2962 0x0400>,

					 <&apps_smmu 0x1982 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent;

		};
@@ -1386,7 +1386,7 @@ 
			iommus = <&apps_smmu 0x2963 0x0400>,

					 <&apps_smmu 0x1983 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent;

		};
@@ -1396,7 +1396,7 @@ 
			iommus = <&apps_smmu 0x2964 0x0400>,

					 <&apps_smmu 0x1984 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent;

		};
@@ -1406,7 +1406,7 @@ 
			iommus = <&apps_smmu 0x2965 0x0400>,

					 <&apps_smmu 0x1985 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent;

		};
@@ -1416,7 +1416,7 @@ 
			iommus = <&apps_smmu 0x02966 0x0400>,

					 <&apps_smmu 0x1986 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent;

		};
@@ -1426,7 +1426,7 @@ 
			iommus = <&apps_smmu 0x2967 0x0400>,

					 <&apps_smmu 0x1987 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent;

		};
@@ -1436,7 +1436,7 @@ 
			iommus = <&apps_smmu 0x2968 0x0400>,

					 <&apps_smmu 0x1988 0x0420>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent;

		};
@@ -1447,7 +1447,7 @@ 
			iommus = <&apps_smmu 0x2969 0x0400>,

					 <&apps_smmu 0x1989 0x0420>;

			qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			qcom,iommu-vmid = <0xA>;	/* VMID_CP_PIXEL */

			dma-coherent;

		};
@@ -1457,7 +1457,7 @@ 
			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x2003 0x0>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent;

		};
@@ -1466,7 +1466,7 @@ 
			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x2004 0x0>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent;

		};
@@ -1475,7 +1475,7 @@ 
			label = "adsprpc-smd";

			iommus = <&apps_smmu 0x2005 0x0>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent;

		};
@@ -1485,7 +1485,7 @@ 
			iommus = <&apps_smmu 0x198B 0x0420>,

					 <&apps_smmu 0x296B 0x0400>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent;

		};
@@ -1495,7 +1495,7 @@ 
			iommus = <&apps_smmu 0x198C 0x0420>,

					 <&apps_smmu 0x296C 0x0400>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent;

		};
@@ -1505,7 +1505,7 @@ 
			iommus = <&apps_smmu 0x198D 0x0420>,

					 <&apps_smmu 0x296D 0x0400>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent;

		};
@@ -1515,7 +1515,7 @@ 
			iommus = <&apps_smmu 0x198E 0x0420>,

					 <&apps_smmu 0x296E 0x0400>;

			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;

			qcom,iommu-faults = "stall-disable";

			qcom,iommu-faults = "stall-disable", "HUPCF";

			dma-coherent;

		};

	};