Merge tag 'for-linus-20160112' of git://git.infradead.org/linux-mtd

	<sect1 id="Basic_defines">

		<title>Basic defines</title>

		<para>

			At least you have to provide a mtd structure and

			a storage for the ioremap'ed chip address.

			You can allocate the mtd structure using kmalloc

			or you can allocate it statically.

			In case of static allocation you have to allocate

			a nand_chip structure too.

			At least you have to provide a nand_chip structure

			and a storage for the ioremap'ed chip address.

			You can allocate the nand_chip structure using

			kmalloc or you can allocate it statically.

			The NAND chip structure embeds an mtd structure

			which will be registered to the MTD subsystem.

			You can extract a pointer to the mtd structure

			from a nand_chip pointer using the nand_to_mtd()

			helper.

		</para>

		<para>

			Kmalloc based example

			Static example

		</para>

		<programlisting>

static struct mtd_info board_mtd;

static struct nand_chip board_chip;

static void __iomem *baseaddr;

		</programlisting>

		<programlisting>

static void board_hwcontrol(struct mtd_info *mtd, int cmd)

{

	struct nand_chip *this = (struct nand_chip *) mtd->priv;

	struct nand_chip *this = mtd_to_nand(mtd);

	switch(cmd){

		case NAND_CTL_SETCLE: this->IO_ADDR_W |= CLE_ADRR_BIT;  break;

		case NAND_CTL_CLRCLE: this->IO_ADDR_W &= ~CLE_ADRR_BIT; break;

	int err = 0;

	/* Allocate memory for MTD device structure and private data */

	board_mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);

	if (!board_mtd) {

	this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);

	if (!this) {

		printk ("Unable to allocate NAND MTD device structure.\n");

		err = -ENOMEM;

		goto out;

	}

	board_mtd = nand_to_mtd(this);

	/* map physical address */

	baseaddr = ioremap(CHIP_PHYSICAL_ADDRESS, 1024);

	if (!baseaddr) {

		goto out_mtd;

	}

	/* Get pointer to private data */

	this = (struct nand_chip *) ();

	/* Link the private data with the MTD structure */

	board_mtd->priv = this;

	/* Set address of NAND IO lines */

	this->IO_ADDR_R = baseaddr;

	this->IO_ADDR_W = baseaddr;

out_ior:

	iounmap(baseaddr);

out_mtd:

	kfree (board_mtd);

	kfree (this);

out:

	return err;

}

	iounmap(baseaddr);

	/* Free the MTD device structure */

	kfree (board_mtd);

	kfree (mtd_to_nand(board_mtd));

}

module_exit(board_cleanup);

#endif

		<programlisting>

static void board_select_chip (struct mtd_info *mtd, int chip)

{

	struct nand_chip *this = (struct nand_chip *) mtd->priv;

	struct nand_chip *this = mtd_to_nand(mtd);

	/* Deselect all chips */

	this->IO_ADDR_R &= ~BOARD_NAND_ADDR_MASK;

- #size-cells      : <0>

Optional properties:

- clock                     : reference to the clock for the NAND controller

- clock-names               : "nand" (required for the above clock)

- brcm,nand-has-wp          : Some versions of this IP include a write-protect

                              (WP) control bit. It is always available on >=

                              v7.0. Use this property to describe the rare

       and enable registers

     - reg-names: (required) "nand-int-base"

   * "brcm,nand-bcm6368"

     - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"

     - reg: (required) the 'NAND_INTR_BASE' register range, with combined status

       and enable registers, and boot address registers

     - reg-names: (required) "nand-int-base"

   * "brcm,nand-iproc"

     - reg: (required) the "IDM" register range, for interrupt enable and APB

       bus access endianness configuration, and the "EXT" register range,

		};

	};

};

nand@10000200 {

	compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",

		"brcm,brcmnand-v4.0", "brcm,brcmnand";

	reg = <0x10000200 0x180>,

	      <0x10000600 0x200>,

	      <0x100000b0 0x10>;

	reg-names = "nand", "nand-cache", "nand-int-base";

	interrupt-parent = <&periph_intc>;

	interrupts = <50>;

	clocks = <&periph_clk 20>;

	clock-names = "nand";

	#address-cells = <1>;

	#size-cells = <0>;

	nand0: nandcs@0 {

		compatible = "brcm,nandcs";

		reg = <0>;

		nand-on-flash-bbt;

		nand-ecc-strength = <1>;

		nand-ecc-step-size = <512>;

	};

};

* Ingenic JZ4780 NAND/BCH

This file documents the device tree bindings for NAND flash devices on the

JZ4780. NAND devices are connected to the NEMC controller (described in

memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must

be children of the NEMC node.

Required NAND controller device properties:

- compatible: Should be set to "ingenic,jz4780-nand".

- reg: For each bank with a NAND chip attached, should specify a bank number,

  an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank).

Optional NAND controller device properties:

- ingenic,bch-controller: To make use of the hardware BCH controller, this

  property must contain a phandle for the BCH controller node. The required

  properties for this node are described below. If this is not specified,

  software BCH will be used instead.

Optional children nodes:

- Individual NAND chips are children of the NAND controller node.

Required children node properties:

- reg: An integer ranging from 1 to 6 representing the CS line to use.

Optional children node properties:

- nand-ecc-step-size: ECC block size in bytes.

- nand-ecc-strength: ECC strength (max number of correctable bits).

- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default

- nand-on-flash-bbt: boolean to enable on flash bbt option, if not present false

- rb-gpios: GPIO specifier for the busy pin.

- wp-gpios: GPIO specifier for the write protect pin.

Optional child node of NAND chip nodes:

- partitions: see Documentation/devicetree/bindings/mtd/partition.txt

Example:

nemc: nemc@13410000 {

	...

	nandc: nand-controller@1 {

		compatible = "ingenic,jz4780-nand";

		reg = <1 0 0x1000000>;	/* Bank 1 */

		#address-cells = <1>;

		#size-cells = <0>;

		ingenic,bch-controller = <&bch>;

		nand@1 {

			reg = <1>;

			nand-ecc-step-size = <1024>;

			nand-ecc-strength = <24>;

			nand-ecc-mode = "hw";

			nand-on-flash-bbt;

			rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>;

			wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>;

			partitions {

				#address-cells = <2>;

				#size-cells = <2>;

				...

			}

		};

	};

};

The BCH controller is a separate SoC component used for error correction on

NAND devices. The following is a description of the device properties for a

BCH controller.

Required BCH properties:

- compatible: Should be set to "ingenic,jz4780-bch".

- reg: Should specify the BCH controller registers location and length.

- clocks: Clock for the BCH controller.

Example:

bch: bch@134d0000 {

	compatible = "ingenic,jz4780-bch";

	reg = <0x134d0000 0x10000>;

	clocks = <&cgu JZ4780_CLK_BCH>;

};

* MTD SPI driver for ST M25Pxx (and similar) serial flash chips

* SPI NOR flash: ST M25Pxx (and similar) serial flash chips

Required properties:

- #address-cells, #size-cells : Must be present if the device has sub-nodes

  representing partitions.

- compatible : May include a device-specific string consisting of the

               manufacturer and name of the chip. Bear in mind the DT binding

               is not Linux-only, but in case of Linux, see the "m25p_ids"

               table in drivers/mtd/devices/m25p80.c for the list of supported

               chips.

               manufacturer and name of the chip. A list of supported chip

               names follows.

               Must also include "jedec,spi-nor" for any SPI NOR flash that can

               be identified by the JEDEC READ ID opcode (0x9F).

               Supported chip names:

                 at25df321a

                 at25df641

                 at26df081a

                 mr25h256

                 mx25l4005a

                 mx25l1606e

                 mx25l6405d

                 mx25l12805d

                 mx25l25635e

                 n25q064

                 n25q128a11

                 n25q128a13

                 n25q512a

                 s25fl256s1

                 s25fl512s

                 s25sl12801

                 s25fl008k

                 s25fl064k

                 sst25vf040b

                 m25p40

                 m25p80

                 m25p16

                 m25p32

                 m25p64

                 m25p128

                 w25x80

                 w25x32

                 w25q32

                 w25q32dw

                 w25q80bl

                 w25q128

                 w25q256

               The following chip names have been used historically to

               designate quirky versions of flash chips that do not support the

               JEDEC READ ID opcode (0x9F):

                 m25p05-nonjedec

                 m25p10-nonjedec

                 m25p20-nonjedec

                 m25p40-nonjedec

                 m25p80-nonjedec

                 m25p16-nonjedec

                 m25p32-nonjedec

                 m25p64-nonjedec

                 m25p128-nonjedec

- reg : Chip-Select number

- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at

* Serial NOR flash controller for MTK MT81xx (and similar)

Required properties:

- compatible: 	  should be "mediatek,mt8173-nor";

- reg: 		  physical base address and length of the controller's register

- clocks: 	  the phandle of the clocks needed by the nor controller

- clock-names: 	  the names of the clocks

		  the clocks should be named "spi" and "sf". "spi" is used for spi bus,

		  and "sf" is used for controller, these are the clocks witch

		  hardware needs to enabling nor flash and nor flash controller.

		  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.

- #address-cells: should be <1>

- #size-cells:	  should be <0>

The SPI flash must be a child of the nor_flash node and must have a

compatible property. Also see jedec,spi-nor.txt.

Required properties:

- compatible:	  May include a device-specific string consisting of the manufacturer

		  and name of the chip. Must also include "jedec,spi-nor" for any

		  SPI NOR flash that can be identified by the JEDEC READ ID opcode (0x9F).

- reg :		  Chip-Select number

Example:

nor_flash: spi@1100d000 {

	compatible = "mediatek,mt8173-nor";

	reg = <0 0x1100d000 0 0xe0>;

	clocks = <&pericfg CLK_PERI_SPI>,

		 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;

	clock-names = "spi", "sf";

	#address-cells = <1>;

	#size-cells = <0>;

	status = "disabled";

	flash@0 {

		compatible = "jedec,spi-nor";

		reg = <0>;

	};

};