Commit ac0c0b61 authored Apr 23, 2018 by zain wang Committed by Andrzej Hajda Apr 24, 2018

drm/bridge: analogix_dp: Don't use ANALOGIX_DP_PLL_CTL to control pll



There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg
list.  We should use BIT_4 in ANALOGIX_DP_PD to control the pll power
instead of ANALOGIX_DP_PLL_CTL.

Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: zain wang <wzz@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180423105003.9004-15-enric.balletbo@collabora.com

parent 2a7b44c5

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

+12 −8

Original line number	Diff line number	Diff line
		@@ -230,16 +230,20 @@ enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
		void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
		{
		u32 reg;
		u32 mask = DP_PLL_PD;
		u32 pd_addr = ANALOGIX_DP_PLL_CTL;

		if (enable) {
		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
		reg \|= DP_PLL_PD;
		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
		} else {
		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
		reg &= ~DP_PLL_PD;
		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
		if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
		pd_addr = ANALOGIX_DP_PD;
		mask = RK_PLL_PD;
		}

		reg = readl(dp->reg_base + pd_addr);
		if (enable)
		reg \|= mask;
		else
		reg &= ~mask;
		writel(reg, dp->reg_base + pd_addr);
		}

		void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,