Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit abe3265a authored by Chris Metcalf's avatar Chris Metcalf
Browse files

tile: do less L1 I-cache eviction 



We had been doing an automatic full eviction of the L1 I$
everywhere whenever we did a kernel-space TLB flush.  It turns
out this isn't necessary, since all the callers already handle
doing a flush if necessary.

Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
parent 6f0142d5

arch/tile/kernel/tlb.c

+7 −1
Original line number Diff line number Diff line
@@ -91,8 +91,14 @@ void flush_tlb_all(void) 
	}

}



/*

 * Callers need to flush the L1I themselves if necessary, e.g. for

 * kernel module unload.  Otherwise we assume callers are not using

 * executable pgprot_t's.  Using EVICT_L1I means that dataplane cpus

 * will get an unnecessary interrupt otherwise.

 */

void flush_tlb_kernel_range(unsigned long start, unsigned long end)

{

	flush_remote(0, HV_FLUSH_EVICT_L1I, cpu_online_mask,

	flush_remote(0, 0, NULL,

		     start, end - start, PAGE_SIZE, cpu_online_mask, NULL, 0);

}