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Commit ab6cb81d authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 5.4.210 into android11-5.4-lts 



Changes in 5.4.210
	thermal: Fix NULL pointer dereferences in of_thermal_ functions
	ACPI: video: Force backlight native for some TongFang devices
	ACPI: video: Shortening quirk list by identifying Clevo by board_name only
	ACPI: APEI: Better fix to avoid spamming the console with old error logs
	bpf: Verifer, adjust_scalar_min_max_vals to always call update_reg_bounds()
	selftests/bpf: Extend verifier and bpf_sock tests for dst_port loads
	bpf: Test_verifier, #70 error message updates for 32-bit right shift
	selftests/bpf: Fix test_align verifier log patterns
	selftests/bpf: Fix "dubious pointer arithmetic" test
	KVM: Don't null dereference ops->destroy
	selftests: KVM: Handle compiler optimizations in ucall
	media: v4l2-mem2mem: Apply DST_QUEUE_OFF_BASE on MMAP buffers across ioctls
	macintosh/adb: fix oob read in do_adb_query() function
	x86/speculation: Add RSB VM Exit protections
	x86/speculation: Add LFENCE to RSB fill sequence
	Linux 5.4.210

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
Change-Id: I64982119920496f2849c00005fbc654179daa21f
parents cc62c7de de0cd3ea

Documentation/admin-guide/hw-vuln/spectre.rst

+8 −0
Original line number Diff line number Diff line
@@ -422,6 +422,14 @@ The possible values in this file are: 
  'RSB filling'   Protection of RSB on context switch enabled

  =============   ===========================================



  - EIBRS Post-barrier Return Stack Buffer (PBRSB) protection status:



  ===========================  =======================================================

  'PBRSB-eIBRS: SW sequence'   CPU is affected and protection of RSB on VMEXIT enabled

  'PBRSB-eIBRS: Vulnerable'    CPU is vulnerable

  'PBRSB-eIBRS: Not affected'  CPU is not affected by PBRSB

  ===========================  =======================================================



Full mitigation might require a microcode update from the CPU

vendor. When the necessary microcode is not available, the kernel will

report vulnerability.

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 5

PATCHLEVEL = 4

SUBLEVEL = 209

SUBLEVEL = 210

EXTRAVERSION =

NAME = Kleptomaniac Octopus

arch/x86/include/asm/cpufeatures.h

+2 −0
Original line number Diff line number Diff line
@@ -286,6 +286,7 @@ 
#define X86_FEATURE_CQM_MBM_LOCAL	(11*32+ 3) /* LLC Local MBM monitoring */

#define X86_FEATURE_FENCE_SWAPGS_USER	(11*32+ 4) /* "" LFENCE in user entry SWAPGS path */

#define X86_FEATURE_FENCE_SWAPGS_KERNEL	(11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */

#define X86_FEATURE_RSB_VMEXIT_LITE	(11*32+ 6) /* "" Fill RSB on VM exit when EIBRS is enabled */



/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */

#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
@@ -406,5 +407,6 @@ 
#define X86_BUG_ITLB_MULTIHIT		X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */

#define X86_BUG_SRBDS			X86_BUG(24) /* CPU may leak RNG bits if not mitigated */

#define X86_BUG_MMIO_STALE_DATA		X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */

#define X86_BUG_EIBRS_PBRSB		X86_BUG(26) /* EIBRS is vulnerable to Post Barrier RSB Predictions */



#endif /* _ASM_X86_CPUFEATURES_H */

arch/x86/include/asm/msr-index.h

+4 −0
Original line number Diff line number Diff line
@@ -129,6 +129,10 @@ 
						 * bit available to control VERW

						 * behavior.

						 */

#define ARCH_CAP_PBRSB_NO		BIT(24)	/*

						 * Not susceptible to Post-Barrier

						 * Return Stack Buffer Predictions.

						 */



#define MSR_IA32_FLUSH_CMD		0x0000010b

#define L1D_FLUSH			BIT(0)	/*

arch/x86/include/asm/nospec-branch.h

+18 −1
Original line number Diff line number Diff line
@@ -61,7 +61,16 @@ 
774:						\

	dec	reg;				\

	jnz	771b;				\

	add	$(BITS_PER_LONG/8) * nr, sp;

	add	$(BITS_PER_LONG/8) * nr, sp;	\

	/* barrier for jnz misprediction */	\

	lfence;



#define __ISSUE_UNBALANCED_RET_GUARD(sp)	\

	call	881f;				\

	int3;					\

881:						\

	add	$(BITS_PER_LONG/8), sp;		\

	lfence;



#ifdef __ASSEMBLY__
@@ -130,6 +139,14 @@ 
#else

	call	*\reg

#endif

.endm



.macro ISSUE_UNBALANCED_RET_GUARD ftr:req

	ANNOTATE_NOSPEC_ALTERNATIVE

	ALTERNATIVE "jmp .Lskip_pbrsb_\@",				\

		__stringify(__ISSUE_UNBALANCED_RET_GUARD(%_ASM_SP))	\

		\ftr

.Lskip_pbrsb_\@:

.endm



 /*