iwlagn: move rx transport functions to iwl-trans-rx-pcie.c (ab697a9f) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/net/wireless/iwlwifi/Makefile

+1 −1

Original line number	Diff line number	Diff line
		@@ -14,7 +14,7 @@ iwlagn-objs += iwl-6000.o
		iwlagn-objs += iwl-1000.o
		iwlagn-objs += iwl-2000.o
		iwlagn-objs += iwl-pci.o
		iwlagn-objs += iwl-trans.o
		iwlagn-objs += iwl-trans.o iwl-trans-rx-pcie.o

		iwlagn-$(CONFIG_IWLWIFI_DEBUGFS) += iwl-debugfs.o
		iwlagn-$(CONFIG_IWLWIFI_DEVICE_TRACING) += iwl-devtrace.o

drivers/net/wireless/iwlwifi/iwl-agn-lib.c

+1 −225

Original line number	Diff line number	Diff line
		@@ -628,56 +628,6 @@ struct iwl_mod_params iwlagn_mod_params = {
		/* the rest are 0 by default */
		};

		int iwlagn_rx_init(struct iwl_priv priv, struct iwl_rx_queue rxq)
		{
		u32 rb_size;
		const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
		u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */

		rb_timeout = RX_RB_TIMEOUT;

		if (iwlagn_mod_params.amsdu_size_8K)
		rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
		else
		rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;

		/* Stop Rx DMA */
		iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);

		/* Reset driver's Rx queue write index */
		iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);

		/* Tell device where to find RBD circular buffer in DRAM */
		iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
		(u32)(rxq->bd_dma >> 8));

		/* Tell device where in DRAM to update its Rx status */
		iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
		rxq->rb_stts_dma >> 4);

		/* Enable Rx DMA
		* FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
		* the credit mechanism in 5000 HW RX FIFO
		* Direct rx interrupts to hosts
		* Rx buffer size 4 or 8k
		* RB timeout 0x10
		* 256 RBDs
		*/
		iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
		FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL \|
		FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY \|
		FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL \|
		FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK \|
		rb_size\|
		(rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)\|
		(rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));

		/* Set interrupt coalescing timer to default (2048 usecs) */
		iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);

		return 0;
		}

		static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
		{
		/*
		@@ -695,10 +645,10 @@ static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
		~APMG_PS_CTRL_MSK_PWR_SRC);
		}

		/TODO: this function should move to transport layer /
		int iwlagn_hw_nic_init(struct iwl_priv *priv)
		{
		unsigned long flags;
		struct iwl_rx_queue *rxq = &priv->rxq;

		/* nic_init */
		spin_lock_irqsave(&priv->lock, flags);
		@@ -716,17 +666,6 @@ int iwlagn_hw_nic_init(struct iwl_priv *priv)
		/* Allocate the RX queue, or reset if it is already allocated */
		trans_rx_init(priv);

		iwlagn_rx_replenish(priv);

		iwlagn_rx_init(priv, rxq);

		spin_lock_irqsave(&priv->lock, flags);

		rxq->need_update = 1;
		iwl_rx_queue_update_write_ptr(priv, rxq);

		spin_unlock_irqrestore(&priv->lock, flags);

		/* Allocate or reset and init all Tx and Command queues */
		if (trans_tx_init(priv))
		return -ENOMEM;
		@@ -742,169 +681,6 @@ int iwlagn_hw_nic_init(struct iwl_priv *priv)
		return 0;
		}

		/**
		* iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
		*/
		static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
		dma_addr_t dma_addr)
		{
		return cpu_to_le32((u32)(dma_addr >> 8));
		}

		/**
		* iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
		*
		* If there are slots in the RX queue that need to be restocked,
		* and we have free pre-allocated buffers, fill the ranks as much
		* as we can, pulling from rx_free.
		*
		* This moves the 'write' index forward to catch up with 'processed', and
		* also updates the memory address in the firmware to reference the new
		* target buffer.
		*/
		void iwlagn_rx_queue_restock(struct iwl_priv *priv)
		{
		struct iwl_rx_queue *rxq = &priv->rxq;
		struct list_head *element;
		struct iwl_rx_mem_buffer *rxb;
		unsigned long flags;

		spin_lock_irqsave(&rxq->lock, flags);
		while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
		/* The overwritten rxb must be a used one */
		rxb = rxq->queue[rxq->write];
		BUG_ON(rxb && rxb->page);

		/* Get next free Rx buffer, remove from free list */
		element = rxq->rx_free.next;
		rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
		list_del(element);

		/* Point to Rx buffer via next RBD in circular buffer */
		rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
		rxb->page_dma);
		rxq->queue[rxq->write] = rxb;
		rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
		rxq->free_count--;
		}
		spin_unlock_irqrestore(&rxq->lock, flags);
		/* If the pre-allocated buffer pool is dropping low, schedule to
		* refill it */
		if (rxq->free_count <= RX_LOW_WATERMARK)
		queue_work(priv->workqueue, &priv->rx_replenish);


		/* If we've added more space for the firmware to place data, tell it.
		* Increment device's write pointer in multiples of 8. */
		if (rxq->write_actual != (rxq->write & ~0x7)) {
		spin_lock_irqsave(&rxq->lock, flags);
		rxq->need_update = 1;
		spin_unlock_irqrestore(&rxq->lock, flags);
		iwl_rx_queue_update_write_ptr(priv, rxq);
		}
		}

		/**
		* iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
		*
		* When moving to rx_free an SKB is allocated for the slot.
		*
		* Also restock the Rx queue via iwl_rx_queue_restock.
		* This is called as a scheduled work item (except for during initialization)
		*/
		void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
		{
		struct iwl_rx_queue *rxq = &priv->rxq;
		struct list_head *element;
		struct iwl_rx_mem_buffer *rxb;
		struct page *page;
		unsigned long flags;
		gfp_t gfp_mask = priority;

		while (1) {
		spin_lock_irqsave(&rxq->lock, flags);
		if (list_empty(&rxq->rx_used)) {
		spin_unlock_irqrestore(&rxq->lock, flags);
		return;
		}
		spin_unlock_irqrestore(&rxq->lock, flags);

		if (rxq->free_count > RX_LOW_WATERMARK)
		gfp_mask \|= __GFP_NOWARN;

		if (priv->hw_params.rx_page_order > 0)
		gfp_mask \|= __GFP_COMP;

		/* Alloc a new receive buffer */
		page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
		if (!page) {
		if (net_ratelimit())
		IWL_DEBUG_INFO(priv, "alloc_pages failed, "
		"order: %d\n",
		priv->hw_params.rx_page_order);

		if ((rxq->free_count <= RX_LOW_WATERMARK) &&
		net_ratelimit())
		IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
		priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
		rxq->free_count);
		/* We don't reschedule replenish work here -- we will
		* call the restock method and if it still needs
		* more buffers it will schedule replenish */
		return;
		}

		spin_lock_irqsave(&rxq->lock, flags);

		if (list_empty(&rxq->rx_used)) {
		spin_unlock_irqrestore(&rxq->lock, flags);
		__free_pages(page, priv->hw_params.rx_page_order);
		return;
		}
		element = rxq->rx_used.next;
		rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
		list_del(element);

		spin_unlock_irqrestore(&rxq->lock, flags);

		BUG_ON(rxb->page);
		rxb->page = page;
		/* Get physical address of the RB */
		rxb->page_dma = dma_map_page(priv->bus.dev, page, 0,
		PAGE_SIZE << priv->hw_params.rx_page_order,
		DMA_FROM_DEVICE);
		/* dma address must be no more than 36 bits */
		BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
		/* and also 256 byte aligned! */
		BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));

		spin_lock_irqsave(&rxq->lock, flags);

		list_add_tail(&rxb->list, &rxq->rx_free);
		rxq->free_count++;

		spin_unlock_irqrestore(&rxq->lock, flags);
		}
		}

		void iwlagn_rx_replenish(struct iwl_priv *priv)
		{
		unsigned long flags;

		iwlagn_rx_allocate(priv, GFP_KERNEL);

		spin_lock_irqsave(&priv->lock, flags);
		iwlagn_rx_queue_restock(priv);
		spin_unlock_irqrestore(&priv->lock, flags);
		}

		void iwlagn_rx_replenish_now(struct iwl_priv *priv)
		{
		iwlagn_rx_allocate(priv, GFP_ATOMIC);

		iwlagn_rx_queue_restock(priv);
		}

		int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
		{
		int idx = 0;

drivers/net/wireless/iwlwifi/iwl-agn.c

+0 −354

Original line number	Diff line number	Diff line
		@@ -457,346 +457,6 @@ static void iwl_bg_tx_flush(struct work_struct *work)
		iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
		}

		/**
		* iwl_rx_handle - Main entry function for receiving responses from uCode
		*
		* Uses the priv->rx_handlers callback function array to invoke
		* the appropriate handlers, including command responses,
		* frame-received notifications, and other notifications.
		*/
		static void iwl_rx_handle(struct iwl_priv *priv)
		{
		struct iwl_rx_mem_buffer *rxb;
		struct iwl_rx_packet *pkt;
		struct iwl_rx_queue *rxq = &priv->rxq;
		u32 r, i;
		int reclaim;
		unsigned long flags;
		u8 fill_rx = 0;
		u32 count = 8;
		int total_empty;

		/* uCode's read index (stored in shared DRAM) indicates the last Rx
		* buffer that the driver may process (last buffer filled by ucode). */
		r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
		i = rxq->read;

		/* Rx interrupt, but nothing sent from uCode */
		if (i == r)
		IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);

		/* calculate total frames need to be restock after handling RX */
		total_empty = r - rxq->write_actual;
		if (total_empty < 0)
		total_empty += RX_QUEUE_SIZE;

		if (total_empty > (RX_QUEUE_SIZE / 2))
		fill_rx = 1;

		while (i != r) {
		int len;

		rxb = rxq->queue[i];

		/* If an RXB doesn't have a Rx queue slot associated with it,
		* then a bug has been introduced in the queue refilling
		* routines -- catch it here */
		if (WARN_ON(rxb == NULL)) {
		i = (i + 1) & RX_QUEUE_MASK;
		continue;
		}

		rxq->queue[i] = NULL;

		dma_unmap_page(priv->bus.dev, rxb->page_dma,
		PAGE_SIZE << priv->hw_params.rx_page_order,
		DMA_FROM_DEVICE);
		pkt = rxb_addr(rxb);

		IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
		i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);

		len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
		len += sizeof(u32); /* account for status word */
		trace_iwlwifi_dev_rx(priv, pkt, len);

		/* Reclaim a command buffer only if this packet is a response
		* to a (driver-originated) command.
		* If the packet (e.g. Rx frame) originated from uCode,
		* there is no command buffer to reclaim.
		* Ucode should set SEQ_RX_FRAME bit if ucode-originated,
		* but apparently a few don't get set; catch them here. */
		reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
		(pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
		(pkt->hdr.cmd != REPLY_RX) &&
		(pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
		(pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
		(pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
		(pkt->hdr.cmd != REPLY_TX);

		iwl_rx_dispatch(priv, rxb);

		/*
		* XXX: After here, we should always check rxb->page
		* against NULL before touching it or its virtual
		* memory (pkt). Because some rx_handler might have
		* already taken or freed the pages.
		*/

		if (reclaim) {
		/* Invoke any callbacks, transfer the buffer to caller,
		* and fire off the (possibly) blocking
		* trans_send_cmd()
		* as we reclaim the driver command queue */
		if (rxb->page)
		iwl_tx_cmd_complete(priv, rxb);
		else
		IWL_WARN(priv, "Claim null rxb?\n");
		}

		/* Reuse the page if possible. For notification packets and
		* SKBs that fail to Rx correctly, add them back into the
		* rx_free list for reuse later. */
		spin_lock_irqsave(&rxq->lock, flags);
		if (rxb->page != NULL) {
		rxb->page_dma = dma_map_page(priv->bus.dev, rxb->page,
		0, PAGE_SIZE << priv->hw_params.rx_page_order,
		DMA_FROM_DEVICE);
		list_add_tail(&rxb->list, &rxq->rx_free);
		rxq->free_count++;
		} else
		list_add_tail(&rxb->list, &rxq->rx_used);

		spin_unlock_irqrestore(&rxq->lock, flags);

		i = (i + 1) & RX_QUEUE_MASK;
		/* If there are a lot of unused frames,
		* restock the Rx queue so ucode wont assert. */
		if (fill_rx) {
		count++;
		if (count >= 8) {
		rxq->read = i;
		iwlagn_rx_replenish_now(priv);
		count = 0;
		}
		}
		}

		/* Backtrack one entry */
		rxq->read = i;
		if (fill_rx)
		iwlagn_rx_replenish_now(priv);
		else
		iwlagn_rx_queue_restock(priv);
		}

		/* tasklet for iwlagn interrupt */
		void iwl_irq_tasklet(struct iwl_priv *priv)
		{
		u32 inta = 0;
		u32 handled = 0;
		unsigned long flags;
		u32 i;
		#ifdef CONFIG_IWLWIFI_DEBUG
		u32 inta_mask;
		#endif

		spin_lock_irqsave(&priv->lock, flags);

		/* Ack/clear/reset pending uCode interrupts.
		* Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
		*/
		/* There is a hardware bug in the interrupt mask function that some
		* interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
		* they are disabled in the CSR_INT_MASK register. Furthermore the
		* ICT interrupt handling mechanism has another bug that might cause
		* these unmasked interrupts fail to be detected. We workaround the
		* hardware bugs here by ACKing all the possible interrupts so that
		* interrupt coalescing can still be achieved.
		*/
		iwl_write32(priv, CSR_INT, priv->_agn.inta \| ~priv->inta_mask);

		inta = priv->_agn.inta;

		#ifdef CONFIG_IWLWIFI_DEBUG
		if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
		/* just for debug */
		inta_mask = iwl_read32(priv, CSR_INT_MASK);
		IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
		inta, inta_mask);
		}
		#endif

		spin_unlock_irqrestore(&priv->lock, flags);

		/* saved interrupt in inta variable now we can reset priv->_agn.inta */
		priv->_agn.inta = 0;

		/* Now service all interrupt bits discovered above. */
		if (inta & CSR_INT_BIT_HW_ERR) {
		IWL_ERR(priv, "Hardware error detected. Restarting.\n");

		/* Tell the device to stop sending interrupts */
		iwl_disable_interrupts(priv);

		priv->isr_stats.hw++;
		iwl_irq_handle_error(priv);

		handled \|= CSR_INT_BIT_HW_ERR;

		return;
		}

		#ifdef CONFIG_IWLWIFI_DEBUG
		if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
		/* NIC fires this, but we don't use it, redundant with WAKEUP */
		if (inta & CSR_INT_BIT_SCD) {
		IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
		"the frame/frames.\n");
		priv->isr_stats.sch++;
		}

		/* Alive notification via Rx interrupt will do the real work */
		if (inta & CSR_INT_BIT_ALIVE) {
		IWL_DEBUG_ISR(priv, "Alive interrupt\n");
		priv->isr_stats.alive++;
		}
		}
		#endif
		/* Safely ignore these bits for debug checks below */
		inta &= ~(CSR_INT_BIT_SCD \| CSR_INT_BIT_ALIVE);

		/* HW RF KILL switch toggled */
		if (inta & CSR_INT_BIT_RF_KILL) {
		int hw_rf_kill = 0;
		if (!(iwl_read32(priv, CSR_GP_CNTRL) &
		CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
		hw_rf_kill = 1;

		IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
		hw_rf_kill ? "disable radio" : "enable radio");

		priv->isr_stats.rfkill++;

		/* driver only loads ucode once setting the interface up.
		* the driver allows loading the ucode even if the radio
		* is killed. Hence update the killswitch state here. The
		* rfkill handler will care about restarting if needed.
		*/
		if (!test_bit(STATUS_ALIVE, &priv->status)) {
		if (hw_rf_kill)
		set_bit(STATUS_RF_KILL_HW, &priv->status);
		else
		clear_bit(STATUS_RF_KILL_HW, &priv->status);
		wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
		}

		handled \|= CSR_INT_BIT_RF_KILL;
		}

		/* Chip got too hot and stopped itself */
		if (inta & CSR_INT_BIT_CT_KILL) {
		IWL_ERR(priv, "Microcode CT kill error detected.\n");
		priv->isr_stats.ctkill++;
		handled \|= CSR_INT_BIT_CT_KILL;
		}

		/* Error detected by uCode */
		if (inta & CSR_INT_BIT_SW_ERR) {
		IWL_ERR(priv, "Microcode SW error detected. "
		" Restarting 0x%X.\n", inta);
		priv->isr_stats.sw++;
		iwl_irq_handle_error(priv);
		handled \|= CSR_INT_BIT_SW_ERR;
		}

		/* uCode wakes up after power-down sleep */
		if (inta & CSR_INT_BIT_WAKEUP) {
		IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
		iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
		for (i = 0; i < priv->hw_params.max_txq_num; i++)
		iwl_txq_update_write_ptr(priv, &priv->txq[i]);

		priv->isr_stats.wakeup++;

		handled \|= CSR_INT_BIT_WAKEUP;
		}

		/* All uCode command responses, including Tx command responses,
		* Rx "responses" (frame-received notification), and other
		* notifications from uCode come through here*/
		if (inta & (CSR_INT_BIT_FH_RX \| CSR_INT_BIT_SW_RX \|
		CSR_INT_BIT_RX_PERIODIC)) {
		IWL_DEBUG_ISR(priv, "Rx interrupt\n");
		if (inta & (CSR_INT_BIT_FH_RX \| CSR_INT_BIT_SW_RX)) {
		handled \|= (CSR_INT_BIT_FH_RX \| CSR_INT_BIT_SW_RX);
		iwl_write32(priv, CSR_FH_INT_STATUS,
		CSR_FH_INT_RX_MASK);
		}
		if (inta & CSR_INT_BIT_RX_PERIODIC) {
		handled \|= CSR_INT_BIT_RX_PERIODIC;
		iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
		}
		/* Sending RX interrupt require many steps to be done in the
		* the device:
		* 1- write interrupt to current index in ICT table.
		* 2- dma RX frame.
		* 3- update RX shared data to indicate last write index.
		* 4- send interrupt.
		* This could lead to RX race, driver could receive RX interrupt
		* but the shared data changes does not reflect this;
		* periodic interrupt will detect any dangling Rx activity.
		*/

		/* Disable periodic interrupt; we use it as just a one-shot. */
		iwl_write8(priv, CSR_INT_PERIODIC_REG,
		CSR_INT_PERIODIC_DIS);
		iwl_rx_handle(priv);

		/*
		* Enable periodic interrupt in 8 msec only if we received
		* real RX interrupt (instead of just periodic int), to catch
		* any dangling Rx interrupt. If it was just the periodic
		* interrupt, there was no dangling Rx activity, and no need
		* to extend the periodic interrupt; one-shot is enough.
		*/
		if (inta & (CSR_INT_BIT_FH_RX \| CSR_INT_BIT_SW_RX))
		iwl_write8(priv, CSR_INT_PERIODIC_REG,
		CSR_INT_PERIODIC_ENA);

		priv->isr_stats.rx++;
		}

		/* This "Tx" DMA channel is used only for loading uCode */
		if (inta & CSR_INT_BIT_FH_TX) {
		iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
		IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
		priv->isr_stats.tx++;
		handled \|= CSR_INT_BIT_FH_TX;
		/* Wake up uCode load routine, now that load is complete */
		priv->ucode_write_complete = 1;
		wake_up_interruptible(&priv->wait_command_queue);
		}

		if (inta & ~handled) {
		IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
		priv->isr_stats.unhandled++;
		}

		if (inta & ~(priv->inta_mask)) {
		IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
		inta & ~priv->inta_mask);
		}

		/* Re-enable all interrupts */
		/* only Re-enable if disabled by irq */
		if (test_bit(STATUS_INT_ENABLED, &priv->status))
		iwl_enable_interrupts(priv);
		/* Re-enable RF_KILL if it occurred */
		else if (handled & CSR_INT_BIT_RF_KILL)
		iwl_enable_rfkill_int(priv);
		}

		/*****************************************************************************
		*
		* sysfs attributes
		@@ -2321,19 +1981,6 @@ static void iwl_bg_restart(struct work_struct *data)
		}
		}

		static void iwl_bg_rx_replenish(struct work_struct *data)
		{
		struct iwl_priv *priv =
		container_of(data, struct iwl_priv, rx_replenish);

		if (test_bit(STATUS_EXIT_PENDING, &priv->status))
		return;

		mutex_lock(&priv->mutex);
		iwlagn_rx_replenish(priv);
		mutex_unlock(&priv->mutex);
		}

		static int iwl_mac_offchannel_tx(struct ieee80211_hw hw, struct sk_buff skb,
		struct ieee80211_channel *chan,
		enum nl80211_channel_type channel_type,
		@@ -3188,7 +2835,6 @@ static void iwl_setup_deferred_work(struct iwl_priv *priv)
		init_waitqueue_head(&priv->wait_command_queue);

		INIT_WORK(&priv->restart, iwl_bg_restart);
		INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
		INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
		INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
		INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);

drivers/net/wireless/iwlwifi/iwl-agn.h

+0 −6

Original line number	Diff line number	Diff line
		@@ -174,7 +174,6 @@ int iwlagn_hw_valid_rtc_data_addr(u32 addr);
		int iwlagn_send_tx_power(struct iwl_priv *priv);
		void iwlagn_temperature(struct iwl_priv *priv);
		u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv);
		int iwlagn_rx_init(struct iwl_priv priv, struct iwl_rx_queue rxq);
		int iwlagn_hw_nic_init(struct iwl_priv *priv);
		int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv);
		int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control);
		@@ -182,11 +181,6 @@ void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control);
		int iwlagn_send_beacon_cmd(struct iwl_priv *priv);

		/* rx */
		void iwl_irq_tasklet(struct iwl_priv *priv);
		void iwlagn_rx_queue_restock(struct iwl_priv *priv);
		void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority);
		void iwlagn_rx_replenish(struct iwl_priv *priv);
		void iwlagn_rx_replenish_now(struct iwl_priv *priv);
		int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band);
		void iwl_setup_rx_handlers(struct iwl_priv *priv);
		void iwl_rx_dispatch(struct iwl_priv priv, struct iwl_rx_mem_buffer rxb);

drivers/net/wireless/iwlwifi/iwl-core.h

+0 −3

Original line number	Diff line number	Diff line
		@@ -336,9 +336,6 @@ static inline void iwl_update_stats(struct iwl_priv *priv, bool is_tx,
		/*****************************************************
		* RX
		******************************************************/
		void iwl_rx_queue_update_write_ptr(struct iwl_priv *priv,
		struct iwl_rx_queue *q);
		int iwl_rx_queue_space(const struct iwl_rx_queue *q);
		void iwl_tx_cmd_complete(struct iwl_priv priv, struct iwl_rx_mem_buffer rxb);

		void iwl_chswitch_done(struct iwl_priv *priv, bool is_success);