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Commit ab484f8f authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: Remove gen specific checks in MMIO 



Now that MMIO has been split up into gen specific functions it is
obvious when HAS_FPGA_DBG_UNCLAIMED, HAS_FORCE_WAKE are needed. As such,
we can remove this extraneous condition.

As a result of this, as well as previously existing function pointers
for forcewake, we no longer need the has_force_wake member in the device
specific data structure.

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 4032ef43

drivers/gpu/drm/i915/i915_drv.c

+1 −4
Original line number Diff line number Diff line
@@ -257,7 +257,6 @@ static const struct intel_device_info intel_sandybridge_d_info = { 
	.has_bsd_ring = 1,

	.has_blt_ring = 1,

	.has_llc = 1,

	.has_force_wake = 1,

};



static const struct intel_device_info intel_sandybridge_m_info = {
@@ -267,7 +266,6 @@ static const struct intel_device_info intel_sandybridge_m_info = { 
	.has_bsd_ring = 1,

	.has_blt_ring = 1,

	.has_llc = 1,

	.has_force_wake = 1,

};



#define GEN7_FEATURES  \
@@ -275,8 +273,7 @@ static const struct intel_device_info intel_sandybridge_m_info = { 
	.need_gfx_hws = 1, .has_hotplug = 1, \

	.has_bsd_ring = 1, \

	.has_blt_ring = 1, \

	.has_llc = 1, \

	.has_force_wake = 1

	.has_llc = 1



static const struct intel_device_info intel_ivybridge_d_info = {

	GEN7_FEATURES,

drivers/gpu/drm/i915/i915_drv.h

+0 −3
Original line number Diff line number Diff line
@@ -441,7 +441,6 @@ struct intel_uncore { 
	func(is_valleyview) sep \

	func(is_haswell) sep \

	func(is_preliminary) sep \

	func(has_force_wake) sep \

	func(has_fbc) sep \

	func(has_pipe_cxsr) sep \

	func(has_hotplug) sep \
@@ -1729,8 +1728,6 @@ struct drm_i915_file_private { 
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)

#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)



#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)



/* DPF == dynamic parity feature */

#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))

#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))

drivers/gpu/drm/i915/intel_ringbuffer.c

+2 −4
Original line number Diff line number Diff line
@@ -395,7 +395,6 @@ static int init_ring_common(struct intel_ring_buffer *ring) 
	int ret = 0;

	u32 head;



	if (HAS_FORCE_WAKE(dev))

	gen6_gt_force_wake_get(dev_priv);



	if (I915_NEED_GFX_HWS(dev))
@@ -469,7 +468,6 @@ static int init_ring_common(struct intel_ring_buffer *ring) 
	memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));



out:

	if (HAS_FORCE_WAKE(dev))

	gen6_gt_force_wake_put(dev_priv);



	return ret;

drivers/gpu/drm/i915/intel_uncore.c

+9 −7
Original line number Diff line number Diff line
@@ -282,6 +282,9 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 
{

	unsigned long irqflags;



	if (!dev_priv->uncore.funcs.force_wake_get)

		return;



	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);

	if (dev_priv->uncore.forcewake_count++ == 0)

		dev_priv->uncore.funcs.force_wake_get(dev_priv);
@@ -295,6 +298,9 @@ void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 
{

	unsigned long irqflags;



	if (!dev_priv->uncore.funcs.force_wake_put)

		return;



	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);

	if (--dev_priv->uncore.forcewake_count == 0) {

		dev_priv->uncore.forcewake_count++;
@@ -307,9 +313,7 @@ void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 


/* We give fast paths for the really cool registers */

#define NEEDS_FORCE_WAKE(dev_priv, reg) \

	((HAS_FORCE_WAKE((dev_priv)->dev)) && \

	 ((reg) < 0x40000) &&            \

	 ((reg) != FORCEWAKE))

	 ((reg) < 0x40000 && (reg) != FORCEWAKE)



static void

ilk_dummy_write(struct drm_i915_private *dev_priv)
@@ -323,8 +327,7 @@ ilk_dummy_write(struct drm_i915_private *dev_priv) 
static void

hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)

{

	if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&

	    (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {

	if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {

		DRM_ERROR("Unknown unclaimed register before writing to %x\n",

			  reg);

		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
@@ -334,8 +337,7 @@ hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) 
static void

hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)

{

	if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&

	    (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {

	if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {

		DRM_ERROR("Unclaimed write to %x\n", reg);

		__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);

	}