ARM: dts: msm: Add initial device tree for SM8150 (ab09b101) · Commits · e / devices / android_kernel_fairphone_FP5

qcom/sm8150-pinctrl.dtsi

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qcom/sm8150.dtsi

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		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/soc/qcom,rpmh-rsc.h>
		#include <dt-bindings/clock/qcom,rpmh.h>

		/ {
		model = "Qualcomm Technologies, Inc. SM8150";
		compatible = "qcom,sm8150";
		qcom,msm-name = "SM8150 V1";
		qcom,msm-id = <339 0x10000>;
		interrupt-parent = <&intc>;

		#address-cells = <2>;
		#size-cells = <2>;
		memory { device_type = "memory"; reg = <0 0 0 0>; };

		aliases {
		};

		cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,armv8";
		reg = <0x0 0x0>;
		enable-method = "psci";
		capacity-dmips-mhz = <1024>;
		cache-size = <0x8000>;
		next-level-cache = <&L2_0>;
		L2_0: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		cache-level = <2>;
		next-level-cache = <&L3_0>;

		L3_0: l3-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x200000>;
		cache-level = <3>;
		};
		};

		L1_I_0: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x8800>;
		};

		L1_D_0: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9000>;
		};

		L2_TLB_0: l2-tlb {
		qcom,dump-size = <0x5000>;
		};
		};

		CPU1: cpu@100 {
		device_type = "cpu";
		compatible = "arm,armv8";
		reg = <0x0 0x100>;
		enable-method = "psci";
		capacity-dmips-mhz = <1024>;
		cache-size = <0x8000>;
		next-level-cache = <&L2_1>;
		L2_1: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		};

		L1_I_100: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x8800>;
		};

		L1_D_100: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9000>;
		};

		L2_TLB_100: l2-tlb {
		qcom,dump-size = <0x5000>;
		};
		};

		CPU2: cpu@200 {
		device_type = "cpu";
		compatible = "arm,armv8";
		reg = <0x0 0x200>;
		enable-method = "psci";
		capacity-dmips-mhz = <1024>;
		cache-size = <0x8000>;
		next-level-cache = <&L2_2>;
		L2_2: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		};

		L1_I_200: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x8800>;
		};

		L1_D_200: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9000>;
		};

		L2_TLB_200: l2-tlb {
		qcom,dump-size = <0x5000>;
		};
		};

		CPU3: cpu@300 {
		device_type = "cpu";
		compatible = "arm,armv8";
		reg = <0x0 0x300>;
		enable-method = "psci";
		capacity-dmips-mhz = <1024>;
		cache-size = <0x8000>;
		next-level-cache = <&L2_3>;
		L2_3: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x20000>;
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		};

		L1_I_300: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x8800>;
		};

		L1_D_300: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9000>;
		};

		L2_TLB_300: l2-tlb {
		qcom,dump-size = <0x5000>;
		};
		};

		CPU4: cpu@400 {
		device_type = "cpu";
		compatible = "arm,armv8";
		reg = <0x0 0x400>;
		enable-method = "psci";
		capacity-dmips-mhz = <1740>;
		cache-size = <0x20000>;
		next-level-cache = <&L2_4>;
		L2_4: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x40000>;
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		qcom,dump-size = <0x88000>;
		};

		L1_I_400: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x11000>;
		};

		L1_D_400: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};

		L1_ITLB_400: l1-itlb {
		qcom,dump-size = <0x300>;
		};

		L1_DTLB_400: l1-dtlb {
		qcom,dump-size = <0x480>;
		};

		L2_TLB_400: l2-tlb {
		qcom,dump-size = <0x7800>;
		};
		};

		CPU5: cpu@500 {
		device_type = "cpu";
		compatible = "arm,armv8";
		reg = <0x0 0x500>;
		enable-method = "psci";
		capacity-dmips-mhz = <1740>;
		cache-size = <0x20000>;
		next-level-cache = <&L2_5>;
		L2_5: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x40000>;
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		qcom,dump-size = <0x88000>;
		};

		L1_I_500: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x11000>;
		};

		L1_D_500: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};

		L1_ITLB_500: l1-itlb {
		qcom,dump-size = <0x300>;
		};

		L1_DTLB_500: l1-dtlb {
		qcom,dump-size = <0x480>;
		};

		L2_TLB_500: l2-tlb {
		qcom,dump-size = <0x7800>;
		};
		};

		CPU6: cpu@600 {
		device_type = "cpu";
		compatible = "arm,armv8";
		reg = <0x0 0x600>;
		enable-method = "psci";
		capacity-dmips-mhz = <1740>;
		cache-size = <0x20000>;
		next-level-cache = <&L2_6>;
		L2_6: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x40000>;
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		qcom,dump-size = <0x88000>;
		};

		L1_I_600: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x11000>;
		};

		L1_D_600: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};

		L1_ITLB_600: l1-itlb {
		qcom,dump-size = <0x300>;
		};

		L1_DTLB_600: l1-dtlb {
		qcom,dump-size = <0x480>;
		};

		L2_TLB_600: l2-tlb {
		qcom,dump-size = <0x7800>;
		};
		};

		CPU7: cpu@700 {
		device_type = "cpu";
		compatible = "arm,armv8";
		reg = <0x0 0x700>;
		enable-method = "psci";
		capacity-dmips-mhz = <1740>;
		cache-size = <0x20000>;
		next-level-cache = <&L2_7>;
		L2_7: l2-cache {
		compatible = "arm,arch-cache";
		cache-size = <0x80000>;
		cache-level = <2>;
		next-level-cache = <&L3_0>;
		qcom,dump-size = <0x110000>;
		};

		L1_I_700: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x11000>;
		};

		L1_D_700: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};

		L1_ITLB_700: l1-itlb {
		qcom,dump-size = <0x300>;
		};

		L1_DTLB_700: l1-dtlb {
		qcom,dump-size = <0x480>;
		};

		L2_TLB_700: l2-tlb {
		qcom,dump-size = <0x7800>;
		};
		};

		cpu-map {
		cluster0 {
		core0 {
		cpu = <&CPU0>;
		};

		core1 {
		cpu = <&CPU1>;
		};

		core2 {
		cpu = <&CPU2>;
		};

		core3 {
		cpu = <&CPU3>;
		};
		};

		cluster1 {
		core0 {
		cpu = <&CPU4>;
		};

		core1 {
		cpu = <&CPU5>;
		};

		core2 {
		cpu = <&CPU6>;
		};
		};

		cluster2 {
		core0 {
		cpu = <&CPU7>;
		};
		};
		};
		};

		psci {
		compatible = "arm,psci-1.0";
		method = "smc";
		};

		chosen { };

		soc: soc { };

		firmware: firmware { };

		reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hyp_mem: hyp_mem {
		no-map;
		reg = <0x0 0x85700000 0x0 0x600000>;
		};

		xbl_mem: xbl_mem {
		no-map;
		reg = <0x0 0x85e00000 0x0 0x100000>;
		};

		aop_mem: memory@85f00000 {
		reg = <0x0 0x85f00000 0x0 0x20000>;
		no-map;
		};

		aop_cmd_db: memory@85f20000 {
		compatible = "qcom,cmd-db";
		reg = <0x0 0x85f20000 0x0 0x20000>;
		no-map;
		};

		smem_region: smem {
		no-map;
		reg = <0x0 0x86000000 0x0 0x200000>;
		};

		removed_regions: removed_regions {
		no-map;
		reg = <0x0 0x86200000 0x0 0x5500000>;
		};

		pil_camera_mem: camera_region {
		no-map;
		reg = <0x0 0x8b700000 0x0 0x500000>;
		};

		pil_wlan_fw_mem: pil_wlan_fw_region {
		no-map;
		reg = <0x0 0x8bc00000 0x0 0x180000>;
		};

		pil_npu_mem: pil_npu_region {
		no-map;
		reg = <0x0 0x8bd80000 0x0 0x80000>;
		};

		pil_adsp_mem: pil_adsp_region {
		no-map;
		reg = <0x0 0x8be00000 0x0 0x1a00000>;
		};

		pil_modem_mem: modem_region {
		no-map;
		reg = <0x0 0x8d800000 0x0 0x9600000>;
		};

		pil_video_mem: pil_video_region {
		no-map;
		reg = <0x0 0x96e00000 0x0 0x500000>;
		};

		pil_slpi_mem: pil_slpi_region {
		no-map;
		reg = <0x0 0x97300000 0x0 0x1400000>;
		};

		pil_ipa_fw_mem: pil_ipa_fw_region {
		no-map;
		reg = <0x0 0x98700000 0x0 0x10000>;
		};

		pil_ipa_gsi_mem: pil_ipa_gsi_region {
		no-map;
		reg = <0x0 0x98710000 0x0 0x5000>;
		};

		pil_gpu_mem: pil_gpu_region {
		no-map;
		reg = <0x0 0x98715000 0x0 0x2000>;
		};

		pil_spss_mem: pil_spss_region {
		no-map;
		reg = <0x0 0x98800000 0x0 0x100000>;
		};

		pil_cdsp_mem: cdsp_regions {
		no-map;
		reg = <0x0 0x98900000 0x0 0x1400000>;
		};

		qseecom_mem: qseecom_region {
		compatible = "shared-dma-pool";
		no-map;
		reg = <0x0 0x9e400000 0x0 0x1400000>;
		};

		cdsp_sec_mem: cdsp_sec_regions {
		no-map;
		reg = <0x0 0xa4c00000 0x0 0x3c00000>;
		};

		cont_splash_memory: cont_splash_region {
		reg = <0x0 0x9c000000 0x0 0x2400000>;
		label = "cont_splash_region";
		};

		disp_rdump_memory: disp_rdump_region {
		reg = <0x0 0x9c000000 0x0 0x02400000>;
		label = "disp_rdump_region";
		};

		adsp_mem: adsp_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1000000>;
		};

		cdsp_mem: cdsp_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x400000>;
		};

		user_contig_mem: user_contig_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1000000>;
		};

		qseecom_ta_mem: qseecom_ta_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1000000>;
		};

		sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x800000>;
		};

		secure_display_memory: secure_display_region { /* Secure UI */
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0xA000000>;
		};

		dump_mem: mem_dump_region {
		compatible = "shared-dma-pool";
		reusable;
		size = <0 0x2400000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x2800000>;
		linux,cma-default;
		};
		};

		vendor: vendor {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";
		};

		clocks {
		xo_board: xo-board {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <38400000>;
		clock-output-names = "xo_board";
		};

		sleep_clk: sleep-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32764>;
		clock-output-names = "sleep_clk";
		};
		};
		};

		&soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		intc: interrupt-controller@17a00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x17a00000 0x10000>, /* GICD */
		<0x17a60000 0x100000>; /* GICR * 8 */
		interrupts = <1 9 4>;
		interrupt-parent = <&intc>;
		};

		pdc: interrupt-controller@0xb220000 {
		compatible = "qcom,pdc-sm8150";
		reg = <0xb220000 0x400>;
		#interrupt-cells = <3>;
		interrupt-parent = <&intc>;
		interrupt-controller;
		};

		arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
		<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
		<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>,
		<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) \| IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
		};

		timer@0x17c20000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17c20000 0x1000>;
		clock-frequency = <19200000>;

		frame@0x17c21000 {
		frame-number = <0>;
		interrupts = <0 8 0x4>,
		<0 6 0x4>;
		reg = <0x17c21000 0x1000>,
		<0x17c22000 0x1000>;
		};

		frame@17c23000 {
		frame-number = <1>;
		interrupts = <0 9 0x4>;
		reg = <0x17c23000 0x1000>;
		status = "disabled";
		};

		frame@17c25000 {
		frame-number = <2>;
		interrupts = <0 10 0x4>;
		reg = <0x17c25000 0x1000>;
		status = "disabled";
		};

		frame@17c27000 {
		frame-number = <3>;
		interrupts = <0 11 0x4>;
		reg = <0x17c26000 0x1000>;
		status = "disabled";
		};

		frame@17c29000 {
		frame-number = <4>;
		interrupts = <0 12 0x4>;
		reg = <0x17c29000 0x1000>;
		status = "disabled";
		};

		frame@17c2b000 {
		frame-number = <5>;
		interrupts = <0 13 0x4>;
		reg = <0x17c2b000 0x1000>;
		status = "disabled";
		};

		frame@17c2d000 {
		frame-number = <6>;
		interrupts = <0 14 0x4>;
		reg = <0x17c2d000 0x1000>;
		status = "disabled";
		};
		};

		qcom,msm-rtb {
		compatible = "qcom,msm-rtb";
		qcom,rtb-size = <0x100000>;
		};

		apps_rsc: rsc@18200000 {
		label = "apps_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0x18200000 0x10000>,
		<0x18210000 0x10000>,
		<0x18220000 0x10000>;
		reg-names = "drv-0", "drv-1", "drv-2";
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		qcom,tcs-offset = <0xd00>;
		qcom,drv-id = <2>;
		qcom,tcs-config = <ACTIVE_TCS 2>,
		<SLEEP_TCS 1>,
		<WAKE_TCS 1>,
		<CONTROL_TCS 0>;

		rpmhcc: clock-controller {
		compatible = "qcom,sm8150-rpmh-clk";
		#clock-cells = <1>;
		clock-names = "xo";
		clocks = <&xo_board>;
		status = "okay";
		};
		};

		gcc: clock-controller@100000 {
		compatible = "qcom,gcc-sm8150";
		reg = <0x00100000 0x1f0000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		#power-domain-cells = <1>;
		clock-names = "bi_tcxo",
		"sleep_clk";
		clocks = <&rpmhcc RPMH_CXO_CLK>,
		<&sleep_clk>;
		};

		qupv3_id_1: geniqup@ac0000 {
		compatible = "qcom,geni-se-qup";
		reg = <0x00ac0000 0x6000>;
		clock-names = "m-ahb", "s-ahb";
		clocks = <&gcc 123>,
		<&gcc 124>;
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;
		status = "ok";


		uart2: serial@a90000 {
		compatible = "qcom,geni-debug-uart";
		reg = <0x0 0x00a90000 0x0 0x4000>;
		clock-names = "se";
		clocks = <&gcc 105>;
		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
		status = "ok";
		};
		};
		};

		#include "sm8150-pinctrl.dtsi"