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Commit ab046095 authored by Tony Truong's avatar Tony Truong
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ARM: dts: msm: update PCIe LTR value to 150us for sdxlemur 

On sdxlemur, PCIe L1.2 exit is about 150us. Therefore update PCIe
so that it will program all PCI devices LTR register with 150us.
Devices can use this value to deterine if L1.2 should be entered
or not based on their latency requirement.

Change-Id: Ife11959879bd7c09b9cbe256b5e46933124ad6b1
parent f600c83a

qcom/sdxlemur-mtp-mbb.dtsi

+0 −2
Original line number Diff line number Diff line
@@ -30,8 +30,6 @@ 


&pcie0 {

	qcom,boot-option = <0x1>;

	qcom,l1-2-th-scale = <2>; /* 1us */

	qcom,l1-2-th-value = <70>;

};



&pm7250b_vadc {

qcom/sdxlemur-pcie.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -109,6 +109,8 @@ 
			<0x100 &apps_smmu 0x0201 0x1>;



		qcom,aux-clk-freq = <17>; /* 16.6 MHz */

		qcom,l1-2-th-scale = <2>; /* 1us */

		qcom,l1-2-th-value = <150>;

		qcom,eq-fmdc-t-min-phase23 = <1>;

		qcom,slv-addr-space-size = <0x40000000>;

		qcom,ep-latency = <10>;