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Commit aadbf214 authored by Robin Murphy's avatar Robin Murphy Committed by Will Deacon
Browse files

iommu/arm-smmu: Abstract GR1 accesses 



Introduce some register access abstractions which we will later use to
encapsulate various quirks. GR1 is the easiest page to start with.

Signed-off-by: default avatarRobin Murphy <robin.murphy@arm.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 61005762

drivers/iommu/arm-smmu.c

+27 −7
Original line number Diff line number Diff line
@@ -71,7 +71,6 @@ 


/* SMMU global address space */

#define ARM_SMMU_GR0(smmu)		((smmu)->base)

#define ARM_SMMU_GR1(smmu)		((smmu)->base + (1 << (smmu)->pgshift))



/*

 * SMMU global address space with conditional offset to access secure
@@ -250,6 +249,29 @@ struct arm_smmu_domain { 
	struct iommu_domain		domain;

};



static void __iomem *arm_smmu_page(struct arm_smmu_device *smmu, int n)

{

	return smmu->base + (n << smmu->pgshift);

}



static u32 arm_smmu_readl(struct arm_smmu_device *smmu, int page, int offset)

{

	return readl_relaxed(arm_smmu_page(smmu, page) + offset);

}



static void arm_smmu_writel(struct arm_smmu_device *smmu, int page, int offset,

			    u32 val)

{

	writel_relaxed(val, arm_smmu_page(smmu, page) + offset);

}



#define ARM_SMMU_GR1		1



#define arm_smmu_gr1_read(s, o)		\

	arm_smmu_readl((s), ARM_SMMU_GR1, (o))

#define arm_smmu_gr1_write(s, o, v)	\

	arm_smmu_writel((s), ARM_SMMU_GR1, (o), (v))



struct arm_smmu_option_prop {

	u32 opt;

	const char *prop;
@@ -574,7 +596,6 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) 
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);

	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;

	struct arm_smmu_device *smmu = smmu_domain->smmu;

	void __iomem *gr1_base = ARM_SMMU_GR1(smmu);

	void __iomem *cb_base;



	cb_base = ARM_SMMU_CB(smmu, cfg->cbndx);
@@ -585,7 +606,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) 


	fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);

	iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);

	cbfrsynra = readl_relaxed(gr1_base + ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));

	cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));



	dev_err_ratelimited(smmu->dev,

	"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
@@ -676,7 +697,7 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) 
	bool stage1;

	struct arm_smmu_cb *cb = &smmu->cbs[idx];

	struct arm_smmu_cfg *cfg = cb->cfg;

	void __iomem *cb_base, *gr1_base;

	void __iomem *cb_base;



	cb_base = ARM_SMMU_CB(smmu, idx);
@@ -686,7 +707,6 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) 
		return;

	}



	gr1_base = ARM_SMMU_GR1(smmu);

	stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;



	/* CBA2R */
@@ -699,7 +719,7 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) 
		if (smmu->features & ARM_SMMU_FEAT_VMID16)

			reg |= FIELD_PREP(CBA2R_VMID16, cfg->vmid);



		writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(idx));

		arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBA2R(idx), reg);

	}



	/* CBAR */
@@ -718,7 +738,7 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) 
		/* 8-bit VMIDs live in CBAR */

		reg |= FIELD_PREP(CBAR_VMID, cfg->vmid);

	}

	writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(idx));

	arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(idx), reg);



	/*

	 * TCR