ARM: dts: msm: Add edac node for Lahaina SoC

Add edac node with compatibility of arm,arm64-kryo-cpu-erp,
to enable error reporting capability for L1/L2 & L3 memories
on Lahaina SoC.

Change-Id: Id561334e40c0aaf04348db90df4a30252ded2432

parent 44bcfde3

qcom/lahaina.dtsi

+7 −0

Original line number	Diff line number	Diff line
		@@ -612,6 +612,13 @@

		status = "disabled";
		};

		kryo-erp {
		compatible = "arm,arm64-kryo-cpu-erp";
		interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "l1-l2-faultirq","l3-scu-faultirq";
		};
		};

		#include "lahaina-pinctrl.dtsi"