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Commit aa76d43b authored by Huixian Ma's avatar Huixian Ma Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add jtag_mm nodes for monaco 

Enable jtag_mm nodes to support cpu etm save/restore feature.

Change-Id: I840df2bd17547432123dac84b10b8b7bf32b324c
parent 3c2dc17f

qcom/monaco.dtsi

+44 −0
Original line number Original line Diff line number Diff line
@@ -1122,6 +1122,50 @@ 
		};

		};

	};

	};





	jtag_mm0: jtagmm@9040000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9040000 0x1000>;

		reg-names = "etm-base";



		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

	};



	jtag_mm1: jtagmm@9140000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9140000 0x1000>;

		reg-names = "etm-base";



		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU1>;

	};



	jtag_mm2: jtagmm@9240000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9240000 0x1000>;

		reg-names = "etm-base";



		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU2>;

	};



	jtag_mm3: jtagmm@9340000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9340000 0x1000>;

		reg-names = "etm-base";



		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU3>;

	};



	clk_virt: interconnect {

	clk_virt: interconnect {

		compatible = "qcom,monaco-clk_virt";

		compatible = "qcom,monaco-clk_virt";

		#interconnect-cells = <1>;

		#interconnect-cells = <1>;