Fixes for system controllers for Atlas/Malta core cards. (aa0980b8) · Commits · e / devices / android_kernel_fairphone_FP5

arch/mips/mips-boards/generic/init.c

+40 −21

Original line number	Original line	Diff line number	Diff line
	/*		/*
	* Carsten Langgaard, carstenl@mips.com		* Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
	* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.		* All rights reserved.
			* Authors: Carsten Langgaard <carstenl@mips.com>
			* Maciej W. Rozycki <macro@mips.com>
	*		*
	* This program is free software; you can distribute it and/or modify it		* This program is free software; you can distribute it and/or modify it
	* under the terms of the GNU General Public License (Version 2) as		* under the terms of the GNU General Public License (Version 2) as
	@@ -22,18 +24,17 @@
	#include <linux/string.h>		#include <linux/string.h>
	#include <linux/kernel.h>		#include <linux/kernel.h>

	#include <asm/io.h>
	#include <asm/bootinfo.h>		#include <asm/bootinfo.h>
			#include <asm/gt64120.h>
			#include <asm/io.h>
			#include <asm/system.h>

	#include <asm/mips-boards/prom.h>		#include <asm/mips-boards/prom.h>
	#include <asm/mips-boards/generic.h>		#include <asm/mips-boards/generic.h>
	#ifdef CONFIG_MIPS_GT64120
	#include <asm/gt64120.h>
	#endif
	#include <asm/mips-boards/msc01_pci.h>
	#include <asm/mips-boards/bonito64.h>		#include <asm/mips-boards/bonito64.h>
	#ifdef CONFIG_MIPS_MALTA		#include <asm/mips-boards/msc01_pci.h>

	#include <asm/mips-boards/malta.h>		#include <asm/mips-boards/malta.h>
	#endif

	#ifdef CONFIG_KGDB		#ifdef CONFIG_KGDB
	extern int rs_kgdb_hook(int, int);		extern int rs_kgdb_hook(int, int);
	@@ -225,6 +226,8 @@ void __init kgdb_config (void)

	void __init prom_init(void)		void __init prom_init(void)
	{		{
			u32 start, map, mask, data;

	prom_argc = fw_arg0;		prom_argc = fw_arg0;
	_prom_argv = (int *) fw_arg1;		_prom_argv = (int *) fw_arg1;
	_prom_envp = (int *) fw_arg2;		_prom_envp = (int *) fw_arg2;
	@@ -266,12 +269,15 @@ void __init prom_init(void)
	#else		#else
	GT_WRITE(GT_PCI0_CMD_OFS, 0);		GT_WRITE(GT_PCI0_CMD_OFS, 0);
	#endif		#endif
			/* Fix up PCI I/O mapping if necessary (for Atlas). */
			start = GT_READ(GT_PCI0IOLD_OFS);
			map = GT_READ(GT_PCI0IOREMAP_OFS);
			if ((start & map) != 0) {
			map &= ~start;
			GT_WRITE(GT_PCI0IOREMAP_OFS, map);
			}

	#ifdef CONFIG_MIPS_MALTA
	set_io_port_base(MALTA_GT_PORT_BASE);		set_io_port_base(MALTA_GT_PORT_BASE);
	#else
	set_io_port_base((unsigned long)ioremap(0, 0x20000000));
	#endif
	break;		break;

	case MIPS_REVISION_CORID_CORE_EMUL_BON:		case MIPS_REVISION_CORID_CORE_EMUL_BON:
	@@ -300,11 +306,7 @@ void __init prom_init(void)
	BONITO_BONGENCFG_BYTESWAP;		BONITO_BONGENCFG_BYTESWAP;
	#endif		#endif

	#ifdef CONFIG_MIPS_MALTA
	set_io_port_base(MALTA_BONITO_PORT_BASE);		set_io_port_base(MALTA_BONITO_PORT_BASE);
	#else
	set_io_port_base((unsigned long)ioremap(0, 0x20000000));
	#endif
	break;		break;

	case MIPS_REVISION_CORID_CORE_MSC:		case MIPS_REVISION_CORID_CORE_MSC:
	@@ -312,6 +314,12 @@ void __init prom_init(void)
	case MIPS_REVISION_CORID_CORE_EMUL_MSC:		case MIPS_REVISION_CORID_CORE_EMUL_MSC:
	_pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);		_pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);

			mb();
			MSC_READ(MSC01_PCI_CFG, data);
			MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
			wmb();

			/* Fix up lane swapping. */
	#ifdef CONFIG_CPU_LITTLE_ENDIAN		#ifdef CONFIG_CPU_LITTLE_ENDIAN
	MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);		MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
	#else		#else
	@@ -320,12 +328,23 @@ void __init prom_init(void)
	MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF \|		MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF \|
	MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);		MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
	#endif		#endif
			/* Fix up target memory mapping. */
			MSC_READ(MSC01_PCI_BAR0, mask);
			MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);

			/* Don't handle target retries indefinitely. */
			if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
			MSC01_PCI_CFG_MAXRTRY_MSK)
			data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
			MSC01_PCI_CFG_MAXRTRY_SHF)) \|
			((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
			MSC01_PCI_CFG_MAXRTRY_SHF);

			wmb();
			MSC_WRITE(MSC01_PCI_CFG, data);
			mb();

	#ifdef CONFIG_MIPS_MALTA
	set_io_port_base(MALTA_MSC_PORT_BASE);		set_io_port_base(MALTA_MSC_PORT_BASE);
	#else
	set_io_port_base((unsigned long)ioremap(0, 0x20000000));
	#endif
	break;		break;

	default:		default:

arch/mips/mips-boards/generic/pci.c

+123 −35

Original line number	Original line	Diff line number	Diff line
	/*		/*
	* Carsten Langgaard, carstenl@mips.com		* Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
	* Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.		* All rights reserved.
			* Authors: Carsten Langgaard <carstenl@mips.com>
			* Maciej W. Rozycki <macro@mips.com>
	*		*
	* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)		* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
	*		*
	@@ -19,65 +21,46 @@
	*		*
	* MIPS boards specific PCI support.		* MIPS boards specific PCI support.
	*/		*/
	#include <linux/config.h>
	#include <linux/types.h>		#include <linux/types.h>
	#include <linux/pci.h>		#include <linux/pci.h>
	#include <linux/kernel.h>		#include <linux/kernel.h>
	#include <linux/init.h>		#include <linux/init.h>

	#include <asm/mips-boards/generic.h>
	#include <asm/gt64120.h>		#include <asm/gt64120.h>

			#include <asm/mips-boards/generic.h>
	#include <asm/mips-boards/bonito64.h>		#include <asm/mips-boards/bonito64.h>
	#include <asm/mips-boards/msc01_pci.h>		#include <asm/mips-boards/msc01_pci.h>
	#ifdef CONFIG_MIPS_MALTA
	#include <asm/mips-boards/malta.h>
	#endif

	static struct resource bonito64_mem_resource = {		static struct resource bonito64_mem_resource = {
	.name = "Bonito PCI MEM",		.name = "Bonito PCI MEM",
	.start = 0x10000000UL,
	.end = 0x1bffffffUL,
	.flags = IORESOURCE_MEM,		.flags = IORESOURCE_MEM,
	};		};

	static struct resource bonito64_io_resource = {		static struct resource bonito64_io_resource = {
	.name = "Bonito IO MEM",		.name = "Bonito PCI I/O",
	.start = 0x00002000UL, /* avoid conflicts with YAMON allocated I/O addresses */		.start = 0x00000000UL,
	.end = 0x000fffffUL,		.end = 0x000fffffUL,
	.flags = IORESOURCE_IO,		.flags = IORESOURCE_IO,
	};		};

	static struct resource gt64120_mem_resource = {		static struct resource gt64120_mem_resource = {
	.name = "GT64120 PCI MEM",		.name = "GT-64120 PCI MEM",
	.start = 0x10000000UL,
	.end = 0x1bdfffffUL,
	.flags = IORESOURCE_MEM,		.flags = IORESOURCE_MEM,
	};		};

	static struct resource gt64120_io_resource = {		static struct resource gt64120_io_resource = {
	.name = "GT64120 IO MEM",		.name = "GT-64120 PCI I/O",
	#ifdef CONFIG_MIPS_ATLAS
	.start = 0x18000000UL,
	.end = 0x181fffffUL,
	#endif
	#ifdef CONFIG_MIPS_MALTA
	.start = 0x00002000UL,
	.end = 0x001fffffUL,
	#endif
	.flags = IORESOURCE_IO,		.flags = IORESOURCE_IO,
	};		};

	static struct resource msc_mem_resource = {		static struct resource msc_mem_resource = {
	.name = "MSC PCI MEM",		.name = "MSC PCI MEM",
	.start = 0x10000000UL,
	.end = 0x1fffffffUL,
	.flags = IORESOURCE_MEM,		.flags = IORESOURCE_MEM,
	};		};

	static struct resource msc_io_resource = {		static struct resource msc_io_resource = {
	.name = "MSC IO MEM",		.name = "MSC PCI I/O",
	.start = 0x00002000UL,
	.end = 0x007fffffUL,
	.flags = IORESOURCE_IO,		.flags = IORESOURCE_IO,
	};		};

	@@ -89,7 +72,6 @@ static struct pci_controller bonito64_controller = {
	.pci_ops = &bonito64_pci_ops,		.pci_ops = &bonito64_pci_ops,
	.io_resource = &bonito64_io_resource,		.io_resource = &bonito64_io_resource,
	.mem_resource = &bonito64_mem_resource,		.mem_resource = &bonito64_mem_resource,
	.mem_offset = 0x10000000UL,
	.io_offset = 0x00000000UL,		.io_offset = 0x00000000UL,
	};		};

	@@ -97,21 +79,18 @@ static struct pci_controller gt64120_controller = {
	.pci_ops = &gt64120_pci_ops,		.pci_ops = &gt64120_pci_ops,
	.io_resource = &gt64120_io_resource,		.io_resource = &gt64120_io_resource,
	.mem_resource = &gt64120_mem_resource,		.mem_resource = &gt64120_mem_resource,
	.mem_offset = 0x00000000UL,
	.io_offset = 0x00000000UL,
	};		};

	static struct pci_controller msc_controller = {		static struct pci_controller msc_controller = {
	.pci_ops = &msc_pci_ops,		.pci_ops = &msc_pci_ops,
	.io_resource = &msc_io_resource,		.io_resource = &msc_io_resource,
	.mem_resource = &msc_mem_resource,		.mem_resource = &msc_mem_resource,
	.mem_offset = 0x10000000UL,
	.io_offset = 0x00000000UL,
	};		};

	void __init mips_pcibios_init(void)		void __init mips_pcibios_init(void)
	{		{
	struct pci_controller *controller;		struct pci_controller *controller;
			unsigned long start, end, map, start1, end1, map1, map2, map3, mask;

	switch (mips_revision_corid) {		switch (mips_revision_corid) {
	case MIPS_REVISION_CORID_QED_RM5261:		case MIPS_REVISION_CORID_QED_RM5261:
	@@ -135,24 +114,133 @@ void __init mips_pcibios_init(void)
	/* Perform the write */		/* Perform the write */
	GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));		GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));

			/* Set up resource ranges from the controller's registers. */
			start = GT_READ(GT_PCI0M0LD_OFS);
			end = GT_READ(GT_PCI0M0HD_OFS);
			map = GT_READ(GT_PCI0M0REMAP_OFS);
			end = (end & GT_PCI_HD_MSK) \| (start & ~GT_PCI_HD_MSK);
			start1 = GT_READ(GT_PCI0M1LD_OFS);
			end1 = GT_READ(GT_PCI0M1HD_OFS);
			map1 = GT_READ(GT_PCI0M1REMAP_OFS);
			end1 = (end1 & GT_PCI_HD_MSK) \| (start1 & ~GT_PCI_HD_MSK);
			/* Cannot support multiple windows, use the wider. */
			if (end1 - start1 > end - start) {
			start = start1;
			end = end1;
			map = map1;
			}
			mask = ~(start ^ end);
			/* We don't support remapping with a discontiguous mask. */
			BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
			mask != ~((mask & -mask) - 1));
			gt64120_mem_resource.start = start;
			gt64120_mem_resource.end = end;
			gt64120_controller.mem_offset = (start & mask) - (map & mask);
			/* Addresses are 36-bit, so do shifts in the destinations. */
			gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;
			gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;
			gt64120_mem_resource.end \|= (1 << GT_PCI_DCRM_SHF) - 1;
			gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;

			start = GT_READ(GT_PCI0IOLD_OFS);
			end = GT_READ(GT_PCI0IOHD_OFS);
			map = GT_READ(GT_PCI0IOREMAP_OFS);
			end = (end & GT_PCI_HD_MSK) \| (start & ~GT_PCI_HD_MSK);
			mask = ~(start ^ end);
			/* We don't support remapping with a discontiguous mask. */
			BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
			mask != ~((mask & -mask) - 1));
			gt64120_io_resource.start = map & mask;
			gt64120_io_resource.end = (map & mask) \| ~mask;
			gt64120_controller.io_offset = 0;
			/* Addresses are 36-bit, so do shifts in the destinations. */
			gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;
			gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;
			gt64120_io_resource.end \|= (1 << GT_PCI_DCRM_SHF) - 1;

	controller = &gt64120_controller;		controller = &gt64120_controller;
	break;		break;

	case MIPS_REVISION_CORID_BONITO64:		case MIPS_REVISION_CORID_BONITO64:
	case MIPS_REVISION_CORID_CORE_20K:		case MIPS_REVISION_CORID_CORE_20K:
	case MIPS_REVISION_CORID_CORE_EMUL_BON:		case MIPS_REVISION_CORID_CORE_EMUL_BON:
			/* Set up resource ranges from the controller's registers. */
			map = BONITO_PCIMAP;
			map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>
			BONITO_PCIMAP_PCIMAP_LO0_SHIFT;
			map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>
			BONITO_PCIMAP_PCIMAP_LO1_SHIFT;
			map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>
			BONITO_PCIMAP_PCIMAP_LO2_SHIFT;
			/* Combine as many adjacent windows as possible. */
			map = map1;
			start = BONITO_PCILO0_BASE;
			end = 1;
			if (map3 == map2 + 1) {
			map = map2;
			start = BONITO_PCILO1_BASE;
			end++;
			}
			if (map2 == map1 + 1) {
			map = map1;
			start = BONITO_PCILO0_BASE;
			end++;
			}
			bonito64_mem_resource.start = start;
			bonito64_mem_resource.end = start +
			BONITO_PCIMAP_WINBASE(end) - 1;
			bonito64_controller.mem_offset = start -
			BONITO_PCIMAP_WINBASE(map);

	controller = &bonito64_controller;		controller = &bonito64_controller;
	break;		break;

	case MIPS_REVISION_CORID_CORE_MSC:		case MIPS_REVISION_CORID_CORE_MSC:
	case MIPS_REVISION_CORID_CORE_FPGA2:		case MIPS_REVISION_CORID_CORE_FPGA2:
	case MIPS_REVISION_CORID_CORE_EMUL_MSC:		case MIPS_REVISION_CORID_CORE_EMUL_MSC:
			/* Set up resource ranges from the controller's registers. */
			MSC_READ(MSC01_PCI_SC2PMBASL, start);
			MSC_READ(MSC01_PCI_SC2PMMSKL, mask);
			MSC_READ(MSC01_PCI_SC2PMMAPL, map);
			msc_mem_resource.start = start & mask;
			msc_mem_resource.end = (start & mask) \| ~mask;
			msc_controller.mem_offset = (start & mask) - (map & mask);

			MSC_READ(MSC01_PCI_SC2PIOBASL, start);
			MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
			MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
			msc_io_resource.start = map & mask;
			msc_io_resource.end = (map & mask) \| ~mask;
			msc_controller.io_offset = 0;
			ioport_resource.end = ~mask;

			/* If ranges overlap I/O takes precedence. */
			start = start & mask;
			end = start \| ~mask;
			if ((start >= msc_mem_resource.start &&
			start <= msc_mem_resource.end) \|\|
			(end >= msc_mem_resource.start &&
			end <= msc_mem_resource.end)) {
			/* Use the larger space. */
			start = max(start, msc_mem_resource.start);
			end = min(end, msc_mem_resource.end);
			if (start - msc_mem_resource.start >=
			msc_mem_resource.end - end)
			msc_mem_resource.end = start - 1;
			else
			msc_mem_resource.start = end + 1;
			}

	controller = &msc_controller;		controller = &msc_controller;
	break;		break;
	default:		default:
	return;		return;
	}		}

			if (controller->io_resource->start < 0x00001000UL) /* FIXME */
			controller->io_resource->start = 0x00001000UL;

			iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
	ioport_resource.end = controller->io_resource->end;		ioport_resource.end = controller->io_resource->end;

	register_pci_controller (controller);		register_pci_controller (controller);

arch/mips/pci/ops-bonito64.c

+4 −10

Original line number	Original line	Diff line number	Diff line
	/*		/*
	* Carsten Langgaard, carstenl@mips.com		* Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
	* Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.		* All rights reserved.
			* Authors: Carsten Langgaard <carstenl@mips.com>
			* Maciej W. Rozycki <macro@mips.com>
	*		*
	* This program is free software; you can distribute it and/or modify it		* This program is free software; you can distribute it and/or modify it
	* under the terms of the GNU General Public License (Version 2) as		* under the terms of the GNU General Public License (Version 2) as
	@@ -17,7 +19,6 @@
	*		*
	* MIPS boards specific PCI support.		* MIPS boards specific PCI support.
	*/		*/
	#include <linux/config.h>
	#include <linux/types.h>		#include <linux/types.h>
	#include <linux/pci.h>		#include <linux/pci.h>
	#include <linux/kernel.h>		#include <linux/kernel.h>
	@@ -57,13 +58,6 @@ static int bonito64_pcibios_config_access(unsigned char access_type,
	return -1;		return -1;
	}		}

	#ifdef CONFIG_MIPS_BOARDS_GEN
	if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
	/* MIPS Core boards have Bonito connected as device 17 */
	return -1;
	}
	#endif

	/* Clear cause register bits */		/* Clear cause register bits */
	BONITO_PCICMD \|= (BONITO_PCICMD_MABORT_CLR \|		BONITO_PCICMD \|= (BONITO_PCICMD_MABORT_CLR \|
	BONITO_PCICMD_MTABORT_CLR);		BONITO_PCICMD_MTABORT_CLR);

arch/mips/pci/ops-gt64120.c

+4 −6

Original line number	Original line	Diff line number	Diff line
	/*		/*
	* Carsten Langgaard, carstenl@mips.com		* Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
	* Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.		* All rights reserved.
			* Authors: Carsten Langgaard <carstenl@mips.com>
			* Maciej W. Rozycki <macro@mips.com>
	*		*
	* This program is free software; you can distribute it and/or modify it		* This program is free software; you can distribute it and/or modify it
	* under the terms of the GNU General Public License (Version 2) as		* under the terms of the GNU General Public License (Version 2) as
	@@ -43,10 +45,6 @@ static int gt64120_pcibios_config_access(unsigned char access_type,
	unsigned char busnum = bus->number;		unsigned char busnum = bus->number;
	u32 intr;		u32 intr;

	if ((busnum == 0) && (PCI_SLOT(devfn) == 0))
	/* Galileo itself is devfn 0, don't move it around */
	return -1;

	if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))		if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
	return -1; /* Because of a bug in the galileo (for slot 31). */		return -1; /* Because of a bug in the galileo (for slot 31). */

arch/mips/pci/ops-msc.c

+5 −26

Original line number	Original line	Diff line number	Diff line
	@@ -21,7 +21,6 @@
	* MIPS boards specific PCI support.		* MIPS boards specific PCI support.
	*		*
	*/		*/
	#include <linux/config.h>
	#include <linux/types.h>		#include <linux/types.h>
	#include <linux/pci.h>		#include <linux/pci.h>
	#include <linux/kernel.h>		#include <linux/kernel.h>
	@@ -49,34 +48,17 @@ static int msc_pcibios_config_access(unsigned char access_type,
	struct pci_bus bus, unsigned int devfn, int where, u32 data)		struct pci_bus bus, unsigned int devfn, int where, u32 data)
	{		{
	unsigned char busnum = bus->number;		unsigned char busnum = bus->number;
	unsigned char type;
	u32 intr;		u32 intr;

	#ifdef CONFIG_MIPS_BOARDS_GEN
	if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
	/* MIPS Core boards have SOCit connected as device 17 */
	return -1;
	}
	#endif

	/* Clear status register bits. */		/* Clear status register bits. */
	MSC_WRITE(MSC01_PCI_INTSTAT,		MSC_WRITE(MSC01_PCI_INTSTAT,
	(MSC01_PCI_INTCFG_MA_BIT \| MSC01_PCI_INTCFG_TA_BIT));		(MSC01_PCI_INTCFG_MA_BIT \| MSC01_PCI_INTCFG_TA_BIT));

	/* Setup address */
	if (busnum == 0)
	type = 0; /* Type 0 */
	else
	type = 1; /* Type 1 */

	MSC_WRITE(MSC01_PCI_CFGADDR,		MSC_WRITE(MSC01_PCI_CFGADDR,
	((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) \|		((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) \|
	(PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF)		(PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) \|
	\| (PCI_FUNC(devfn) <<		(PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) \|
	MSC01_PCI_CFGADDR_FNUM_SHF) \| ((where /		((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF)));
	4) <<
	MSC01_PCI_CFGADDR_RNUM_SHF)
	\| (type)));

	/* Perform access */		/* Perform access */
	if (access_type == PCI_ACCESS_WRITE)		if (access_type == PCI_ACCESS_WRITE)
	@@ -86,15 +68,12 @@ static int msc_pcibios_config_access(unsigned char access_type,

	/* Detect Master/Target abort */		/* Detect Master/Target abort */
	MSC_READ(MSC01_PCI_INTSTAT, intr);		MSC_READ(MSC01_PCI_INTSTAT, intr);
	if (intr & (MSC01_PCI_INTCFG_MA_BIT \|		if (intr & (MSC01_PCI_INTCFG_MA_BIT \| MSC01_PCI_INTCFG_TA_BIT)) {
	MSC01_PCI_INTCFG_TA_BIT)) {
	/* Error occurred */		/* Error occurred */

	/* Clear bits */		/* Clear bits */
	MSC_READ(MSC01_PCI_INTSTAT, intr);
	MSC_WRITE(MSC01_PCI_INTSTAT,		MSC_WRITE(MSC01_PCI_INTSTAT,
	(MSC01_PCI_INTCFG_MA_BIT \|		(MSC01_PCI_INTCFG_MA_BIT \| MSC01_PCI_INTCFG_TA_BIT));
	MSC01_PCI_INTCFG_TA_BIT));

	return -1;		return -1;
	}		}