Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a9f4d1b8 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Vinod Koul
Browse files

dmaengine: dw: introduce register mappings for iDMA 32-bit 



The integrated DMA (iDMA 32-bit) is Intel designed DMA controller which
mimics Synopsys Designware DMA. This patch appends the register mappings
for the parts which are slightly different to the DesignWare hardware.

Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent 2d248812

drivers/dma/dw/regs.h

+49 −3
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 *

 * Copyright (C) 2005-2007 Atmel Corporation

 * Copyright (C) 2010-2011 ST Microelectronics

 * Copyright (C) 2016 Intel Corporation

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as
@@ -13,6 +14,8 @@ 
#include <linux/interrupt.h>

#include <linux/dmaengine.h>



#include <linux/io-64-nonatomic-hi-lo.h>



#include "internal.h"



#define DW_DMA_MAX_NR_REQUESTS	16
@@ -86,9 +89,9 @@ struct dw_dma_regs { 
	DW_REG(ID);

	DW_REG(TEST);



	/* reserved */

	DW_REG(__reserved0);

	DW_REG(__reserved1);

	/* iDMA 32-bit support */

	DW_REG(CLASS_PRIORITY0);

	DW_REG(CLASS_PRIORITY1);



	/* optional encoded params, 0x3c8..0x3f7 */

	u32	__reserved;
@@ -100,6 +103,17 @@ struct dw_dma_regs { 


	/* top-level parameters */

	u32	DW_PARAMS;



	/* component ID */

	u32	COMP_TYPE;

	u32	COMP_VERSION;



	/* iDMA 32-bit support */

	DW_REG(FIFO_PARTITION0);

	DW_REG(FIFO_PARTITION1);



	DW_REG(SAI_ERR);

	DW_REG(GLOBAL_CFG);

};



/*
@@ -216,6 +230,33 @@ enum dw_dma_msize { 
/* Bitfields in CFG */

#define DW_CFG_DMA_EN		(1 << 0)



/* iDMA 32-bit support */



/* Bitfields in CTL_HI */

#define IDMA32C_CTLH_BLOCK_TS_MASK	GENMASK(16, 0)

#define IDMA32C_CTLH_BLOCK_TS(x)	((x) & IDMA32C_CTLH_BLOCK_TS_MASK)

#define IDMA32C_CTLH_DONE		(1 << 17)



/* Bitfields in CFG_LO */

#define IDMA32C_CFGL_DST_BURST_ALIGN	(1 << 0)	/* dst burst align */

#define IDMA32C_CFGL_SRC_BURST_ALIGN	(1 << 1)	/* src burst align */

#define IDMA32C_CFGL_CH_DRAIN		(1 << 10)	/* drain FIFO */

#define IDMA32C_CFGL_DST_OPT_BL		(1 << 20)	/* optimize dst burst length */

#define IDMA32C_CFGL_SRC_OPT_BL		(1 << 21)	/* optimize src burst length */



/* Bitfields in CFG_HI */

#define IDMA32C_CFGH_SRC_PER(x)		((x) << 0)

#define IDMA32C_CFGH_DST_PER(x)		((x) << 4)

#define IDMA32C_CFGH_RD_ISSUE_THD(x)	((x) << 8)

#define IDMA32C_CFGH_RW_ISSUE_THD(x)	((x) << 18)

#define IDMA32C_CFGH_SRC_PER_EXT(x)	((x) << 28)	/* src peripheral extension */

#define IDMA32C_CFGH_DST_PER_EXT(x)	((x) << 30)	/* dst peripheral extension */



/* Bitfields in FIFO_PARTITION */

#define IDMA32C_FP_PSIZE_CH0(x)		((x) << 0)

#define IDMA32C_FP_PSIZE_CH1(x)		((x) << 13)

#define IDMA32C_FP_UPDATE		(1 << 26)



enum dw_dmac_flags {

	DW_DMA_IS_CYCLIC = 0,

	DW_DMA_IS_SOFT_LLP = 1,
@@ -296,6 +337,11 @@ static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw) 
#define dma_writel(dw, name, val) \

	dma_writel_native((val), &(__dw_regs(dw)->name))



#define idma32_readq(dw, name)				\

	hi_lo_readq(&(__dw_regs(dw)->name))

#define idma32_writeq(dw, name, val)			\

	hi_lo_writeq((val), &(__dw_regs(dw)->name))



#define channel_set_bit(dw, reg, mask) \

	dma_writel(dw, reg, ((mask) << 8) | (mask))

#define channel_clear_bit(dw, reg, mask) \