Merge tag 'clk-renesas-for-v4.7-tag2' of... (a93fed09) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/clk/Kconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -201,6 +201,7 @@ source "drivers/clk/bcm/Kconfig"
		source "drivers/clk/hisilicon/Kconfig"
		source "drivers/clk/mvebu/Kconfig"
		source "drivers/clk/qcom/Kconfig"
		source "drivers/clk/renesas/Kconfig"
		source "drivers/clk/samsung/Kconfig"
		source "drivers/clk/tegra/Kconfig"
		source "drivers/clk/ti/Kconfig"

drivers/clk/renesas/Kconfig

0 → 100644

+16 −0

Original line number	Diff line number	Diff line
		config CLK_RENESAS_CPG_MSSR
		bool
		default y if ARCH_R8A7795

		config CLK_RENESAS_CPG_MSTP
		bool
		default y if ARCH_R7S72100
		default y if ARCH_R8A73A4
		default y if ARCH_R8A7740
		default y if ARCH_R8A7778
		default y if ARCH_R8A7779
		default y if ARCH_R8A7790
		default y if ARCH_R8A7791
		default y if ARCH_R8A7793
		default y if ARCH_R8A7794
		default y if ARCH_SH73A0

drivers/clk/renesas/Makefile

+14 −12

Original line number	Diff line number	Diff line
		obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
		obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o clk-mstp.o
		obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o clk-mstp.o clk-div6.o
		obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-mstp.o clk-div6.o
		obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o clk-mstp.o
		obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o clk-mstp.o
		obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
		obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
		obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
		obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
		obj-$(CONFIG_ARCH_R8A7795) += renesas-cpg-mssr.o \
		r8a7795-cpg-mssr.o clk-div6.o
		obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-mstp.o clk-div6.o
		obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
		obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o clk-div6.o
		obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-div6.o
		obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
		obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
		obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-div6.o
		obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-div6.o
		obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-div6.o
		obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-div6.o
		obj-$(CONFIG_ARCH_R8A7795) += r8a7795-cpg-mssr.o
		obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-div6.o

		obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o clk-div6.o
		obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o

drivers/clk/renesas/clk-mstp.c

+2 −5

Original line number	Diff line number	Diff line
		@@ -243,9 +243,7 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
		}
		CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);


		#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
		int cpg_mstp_attach_dev(struct generic_pm_domain domain, struct device dev)
		int cpg_mstp_attach_dev(struct generic_pm_domain unused, struct device dev)
		{
		struct device_node *np = dev->of_node;
		struct of_phandle_args clkspec;
		@@ -297,7 +295,7 @@ int cpg_mstp_attach_dev(struct generic_pm_domain domain, struct device dev)
		return error;
		}

		void cpg_mstp_detach_dev(struct generic_pm_domain domain, struct device dev)
		void cpg_mstp_detach_dev(struct generic_pm_domain unused, struct device dev)
		{
		if (!list_empty(&dev->power.subsys_data->clock_list))
		pm_clk_destroy(dev);
		@@ -326,4 +324,3 @@ void __init cpg_mstp_add_clk_domain(struct device_node *np)

		of_genpd_add_provider_simple(np, pd);
		}
		#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */

drivers/clk/renesas/r8a7795-cpg-mssr.c

+30 −4

Original line number	Diff line number	Diff line
		@@ -13,6 +13,7 @@
		*/

		#include <linux/bug.h>
		#include <linux/clk.h>
		#include <linux/clk-provider.h>
		#include <linux/device.h>
		#include <linux/err.h>
		@@ -26,6 +27,7 @@

		#include "renesas-cpg-mssr.h"

		#define CPG_RCKCR 0x240

		enum clk_ids {
		/* Core Clock Outputs exported to DT */
		@@ -50,6 +52,7 @@ enum clk_ids {
		CLK_S3,
		CLK_SDSRC,
		CLK_SSPSRC,
		CLK_RINT,

		/* Module Clocks */
		MOD_CLK_BASE
		@@ -63,8 +66,12 @@ enum r8a7795_clk_types {
		CLK_TYPE_GEN3_PLL3,
		CLK_TYPE_GEN3_PLL4,
		CLK_TYPE_GEN3_SD,
		CLK_TYPE_GEN3_R,
		};

		#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
		DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)

		static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
		/* External Clock Inputs */
		DEF_INPUT("extal", CLK_EXTAL),
		@@ -102,10 +109,10 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
		DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
		DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),

		DEF_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074),
		DEF_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078),
		DEF_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268),
		DEF_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c),
		DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074),
		DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078),
		DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268),
		DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c),

		DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
		DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
		@@ -113,6 +120,11 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
		DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
		DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
		DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),

		DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
		DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),

		DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
		};

		static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
		@@ -139,6 +151,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
		DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
		DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
		DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
		DEF_MOD("rwdt0", 402, R8A7795_CLK_R),
		DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
		DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
		DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
		@@ -148,6 +161,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
		DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
		DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
		DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
		DEF_MOD("pwm", 523, R8A7795_CLK_S3D4),
		DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1),
		DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1),
		DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1),
		@@ -578,6 +592,18 @@ struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
		case CLK_TYPE_GEN3_SD:
		return cpg_sd_clk_register(core, base, __clk_get_name(parent));

		case CLK_TYPE_GEN3_R:
		/* RINT is default. Only if EXTALR is populated, we switch to it */
		value = readl(base + CPG_RCKCR) & 0x3f;

		if (clk_get_rate(clks[CLK_EXTALR])) {
		parent = clks[CLK_EXTALR];
		value \|= BIT(15);
		}

		writel(value, base + CPG_RCKCR);
		break;

		default:
		return ERR_PTR(-EINVAL);
		}