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Commit a8f67f4b authored by Paul Mundt's avatar Paul Mundt
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sh: Add SH7263 CPU support. 



This adds support for the SH7263 (SH-2A) CPU.

This particular CPU is a superset of SH7203, adding some additional
peripheral blocks and hooking up additional (reserved on SH7203)
vectors in the INTC block.

No visibly nasty surprises, yet..

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 47a3eb95

arch/sh/Kconfig

+6 −1
Original line number Diff line number Diff line
@@ -166,6 +166,10 @@ config CPU_SUBTYPE_SH7206 
	bool "Support SH7206 processor"

	select CPU_SH2A



config CPU_SUBTYPE_SH7263

	bool "Support SH7263 processor"

	select CPU_SH2A



# SH-3 Processor Support



config CPU_SUBTYPE_SH7705
@@ -560,7 +564,8 @@ config SH_PCLK_FREQ 
	default "32000000" if CPU_SUBTYPE_SH7722

	default "33333333" if CPU_SUBTYPE_SH7770 || \

			      CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \

			      CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206

			      CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \

			      CPU_SUBTYPE_SH7263

	default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R

	default "66000000" if CPU_SUBTYPE_SH4_202

	default "50000000"

arch/sh/Kconfig.debug

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ config EARLY_SCIF_CONSOLE_PORT 
	default "0xffe00000" if CPU_SUBTYPE_SH7780

	default "0xffea0000" if CPU_SUBTYPE_SH7785

	default "0xfffe8000" if CPU_SUBTYPE_SH7203

	default "0xfffe9800" if CPU_SUBTYPE_SH7206

	default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263

	default "0xf8420000" if CPU_SUBTYPE_SH7619

	default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705

	default "0xa4430000" if CPU_SUBTYPE_SH7720

arch/sh/kernel/cpu/sh2a/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -8,3 +8,4 @@ common-y += $(addprefix ../sh2/, ex.o entry.o) 


obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o

obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o

obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o

arch/sh/kernel/cpu/sh2a/probe.c

+3 −0
Original line number Diff line number Diff line
@@ -22,6 +22,9 @@ int __init detect_cpu_and_cache_system(void) 
	boot_cpu_data.type			= CPU_SH7203;

	/* SH7203 has an FPU.. */

	boot_cpu_data.flags			|= CPU_HAS_FPU;

#elif defined(CONFIG_CPU_SUBTYPE_SH7263)

	boot_cpu_data.type			= CPU_SH7263;

	boot_cpu_data.flags			|= CPU_HAS_FPU;

#elif defined(CONFIG_CPU_SUBTYPE_SH7206)

	boot_cpu_data.type			= CPU_SH7206;

	/* While SH7206 has a DSP.. */

arch/sh/kernel/cpu/sh2a/setup-sh7203.c

+40 −2
Original line number Diff line number Diff line 
/*

 * SH7203 Setup

 * SH7203 and SH7263 Setup

 *

 *  Copyright (C) 2007  Paul Mundt

 *
@@ -41,17 +41,27 @@ enum { 
	SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI,

	SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI,

	SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,



	/* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */

	ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG, ROMDEC_ISEC, ROMDEC_IBUF,

	ROMDEC_IREADY,



	FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,



	SDHI3, SDHI0, SDHI1,



	RTC_ARM, RTC_PRD, RTC_CUP,

	RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, RCAN0_SLE,

	RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, RCAN1_SLE,



	SRC_OVF, SRC_ODFI, SRC_IDEI, IEBI,



	/* interrupt groups */

	PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,

	MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,

	MTU3_ABCD, MTU4_ABCD,

	IIC30, IIC31, IIC32, IIC33, SCIF0, SCIF1, SCIF2, SCIF3,

	SSU0, SSU1, FLCTL, RTC, RCAN0, RCAN1

	SSU0, SSU1, ROMDEC, SDHI, FLCTL, RTC, RCAN0, RCAN1, SRC

};



static struct intc_vect vectors[] __initdata = {
@@ -125,6 +135,20 @@ static struct intc_vect vectors[] __initdata = { 
	INTC_IRQ(RCAN1_ERS, 239), INTC_IRQ(RCAN1_OVR, 240),

	INTC_IRQ(RCAN1_RM0, 241), INTC_IRQ(RCAN1_RM1, 242),

	INTC_IRQ(RCAN1_SLE, 243),



	/* SH7263-specific trash */

#ifdef CONFIG_CPU_SUBTYPE_SH7263

	INTC_IRQ(ROMDEC_ISY, 218), INTC_IRQ(ROMDEC_IERR, 219),

	INTC_IRQ(ROMDEC_IARG, 220), INTC_IRQ(ROMDEC_ISEC, 221),

	INTC_IRQ(ROMDEC_IBUF, 222), INTC_IRQ(ROMDEC_IREADY, 223),



	INTC_IRQ(SDHI3, 228), INTC_IRQ(SDHI0, 229), INTC_IRQ(SDHI1, 230),



	INTC_IRQ(SRC_OVF, 244), INTC_IRQ(SRC_ODFI, 245),

	INTC_IRQ(SRC_IDEI, 246),



	INTC_IRQ(IEBI, 247),

#endif

};



static struct intc_group groups[] __initdata = {
@@ -167,6 +191,13 @@ static struct intc_group groups[] __initdata = { 
		   RCAN0_SLE),

	INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1,

		   RCAN1_SLE),



#ifdef CONFIG_CPU_SUBTYPE_SH7263

	INTC_GROUP(ROMDEC, ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG,

		   ROMDEC_ISEC, ROMDEC_IBUF, ROMDEC_IREADY),

	INTC_GROUP(SDHI, SDHI3, SDHI0, SDHI1),

	INTC_GROUP(SRC, SRC_OVF, SRC_ODFI, SRC_IDEI),

#endif

};



static struct intc_prio_reg prio_registers[] __initdata = {
@@ -184,10 +215,17 @@ static struct intc_prio_reg prio_registers[] __initdata = { 
	{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } },

	{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } },

	{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } },

#ifdef CONFIG_CPU_SUBTYPE_SH7203

	{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,

					      SSI3_SSII, 0 } },

	{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } },

	{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } },

#else

	{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,

					      SSI3_SSII, ROMDEC } },

	{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } },

	{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } },

#endif

};



static struct intc_mask_reg mask_registers[] __initdata = {