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Commit a8acd5a1 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'uniphier-dt-v4.10' of... 

Merge tag 'uniphier-dt-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt

UniPhier ARM SoC DT updates for v4.10

- Add OPP tables to support generic cpufreq driver
- Use more clocks/resets properties
- Misc fixes and cleanups

* tag 'uniphier-dt-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier

:
  ARM: dts: uniphier: make compatible of syscon nodes SoC-specific
  ARM: dts: uniphier: add clocks/resets to EHCI nodes of sLD3 SoC
  ARM: dts: uniphier: remove redundant serial fifo-size properties
  ARM: dts: uniphier: make 32bit SoC DTSI linear
  ARM: dts: uniphier: add CPU clocks and OPP table for PXs2 SoC
  ARM: dts: uniphier: add CPU clocks and OPP table for Pro5 SoC
  ARM: dts: uniphier: increase register region size of sysctrl node

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents c9905f01 13b4a619

arch/arm/boot/dts/uniphier-common32.dtsi

deleted100644 → 0
+0 −199
Original line number Diff line number Diff line 
/*

 * Device Tree Source commonly used by UniPhier ARM SoCs

 *

 * Copyright (C) 2015-2016 Socionext Inc.

 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

 *

 * This file is dual-licensed: you can use it either under the terms

 * of the GPL or the X11 license, at your option. Note that this dual

 * licensing only applies to this file, and not this project as a

 * whole.

 *

 *  a) This file is free software; you can redistribute it and/or

 *     modify it under the terms of the GNU General Public License as

 *     published by the Free Software Foundation; either version 2 of the

 *     License, or (at your option) any later version.

 *

 *     This file is distributed in the hope that it will be useful,

 *     but WITHOUT ANY WARRANTY; without even the implied warranty of

 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 *     GNU General Public License for more details.

 *

 * Or, alternatively,

 *

 *  b) Permission is hereby granted, free of charge, to any person

 *     obtaining a copy of this software and associated documentation

 *     files (the "Software"), to deal in the Software without

 *     restriction, including without limitation the rights to use,

 *     copy, modify, merge, publish, distribute, sublicense, and/or

 *     sell copies of the Software, and to permit persons to whom the

 *     Software is furnished to do so, subject to the following

 *     conditions:

 *

 *     The above copyright notice and this permission notice shall be

 *     included in all copies or substantial portions of the Software.

 *

 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES

 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,

 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 *     OTHER DEALINGS IN THE SOFTWARE.

 */



/include/ "skeleton.dtsi"



/ {

	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	clocks {

		refclk: ref {

			#clock-cells = <0>;

			compatible = "fixed-clock";

		};

	};



	soc: soc {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		interrupt-parent = <&intc>;



		serial0: serial@54006800 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006800 0x40>;

			interrupts = <0 33 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart0>;

			clocks = <&peri_clk 0>;

		};



		serial1: serial@54006900 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006900 0x40>;

			interrupts = <0 35 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart1>;

			clocks = <&peri_clk 1>;

		};



		serial2: serial@54006a00 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006a00 0x40>;

			interrupts = <0 37 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart2>;

			clocks = <&peri_clk 2>;

		};



		serial3: serial@54006b00 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006b00 0x40>;

			interrupts = <0 177 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart3>;

			clocks = <&peri_clk 3>;

		};



		system_bus: system-bus@58c00000 {

			compatible = "socionext,uniphier-system-bus";

			status = "disabled";

			reg = <0x58c00000 0x400>;

			#address-cells = <2>;

			#size-cells = <1>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_system_bus>;

		};



		smpctrl@59800000 {

			compatible = "socionext,uniphier-smpctrl";

			reg = <0x59801000 0x400>;

		};



		mioctrl@59810000 {

			compatible = "socionext,uniphier-mioctrl",

				     "simple-mfd", "syscon";

			reg = <0x59810000 0x800>;



			mio_clk: clock {

				#clock-cells = <1>;

			};



			mio_rst: reset {

				#reset-cells = <1>;

			};

		};



		perictrl@59820000 {

			compatible = "socionext,uniphier-perictrl",

				     "simple-mfd", "syscon";

			reg = <0x59820000 0x200>;



			peri_clk: clock {

				#clock-cells = <1>;

			};



			peri_rst: reset {

				#reset-cells = <1>;

			};

		};



		timer@60000200 {

			compatible = "arm,cortex-a9-global-timer";

			reg = <0x60000200 0x20>;

			interrupts = <1 11 0x104>;

			clocks = <&arm_timer_clk>;

		};



		timer@60000600 {

			compatible = "arm,cortex-a9-twd-timer";

			reg = <0x60000600 0x20>;

			interrupts = <1 13 0x104>;

			clocks = <&arm_timer_clk>;

		};



		intc: interrupt-controller@60001000 {

			compatible = "arm,cortex-a9-gic";

			reg = <0x60001000 0x1000>,

			      <0x60000100 0x100>;

			#interrupt-cells = <3>;

			interrupt-controller;

		};



		soc-glue@5f800000 {

			compatible = "socionext,uniphier-soc-glue",

				     "simple-mfd", "syscon";

			reg = <0x5f800000 0x2000>;



			pinctrl: pinctrl {

				/* specify compatible in each SoC DTSI */

			};

		};



		sysctrl@61840000 {

			compatible = "socionext,uniphier-sysctrl",

				     "simple-mfd", "syscon";

			reg = <0x61840000 0x4000>;



			sys_clk: clock {

				#clock-cells = <1>;

			};



			sys_rst: reset {

				#reset-cells = <1>;

			};

		};

	};

};



/include/ "uniphier-pinctrl.dtsi"

arch/arm/boot/dts/uniphier-ld4.dtsi

+239 −119
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ 
 *     OTHER DEALINGS IN THE SOFTWARE.

 */



/include/ "uniphier-common32.dtsi"

/include/ "skeleton.dtsi"



/ {

	compatible = "socionext,uniphier-ld4";
@@ -61,19 +61,36 @@ 
		};

	};



	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	clocks {

		refclk: ref {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <24576000>;

		};



		arm_timer_clk: arm_timer_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <50000000>;

		};

	};

};



&soc {

	soc {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		interrupt-parent = <&intc>;



		l2: l2-cache@500c0000 {

			compatible = "socionext,uniphier-system-cache";

		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;

			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,

			      <0x506c0000 0x400>;

			interrupts = <0 174 4>, <0 175 4>;

			cache-unified;

			cache-size = <(512 * 1024)>;
@@ -82,6 +99,46 @@ 
			cache-level = <2>;

		};



		serial0: serial@54006800 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006800 0x40>;

			interrupts = <0 33 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart0>;

			clocks = <&peri_clk 0>;

		};



		serial1: serial@54006900 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006900 0x40>;

			interrupts = <0 35 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart1>;

			clocks = <&peri_clk 1>;

		};



		serial2: serial@54006a00 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006a00 0x40>;

			interrupts = <0 37 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart2>;

			clocks = <&peri_clk 2>;

		};



		serial3: serial@54006b00 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006b00 0x40>;

			interrupts = <0 29 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart3>;

			clocks = <&peri_clk 3>;

		};



		i2c0: i2c@58400000 {

			compatible = "socionext,uniphier-i2c";

			status = "disabled";
@@ -134,6 +191,53 @@ 
			clock-frequency = <100000>;

		};



		system_bus: system-bus@58c00000 {

			compatible = "socionext,uniphier-system-bus";

			status = "disabled";

			reg = <0x58c00000 0x400>;

			#address-cells = <2>;

			#size-cells = <1>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_system_bus>;

		};



		smpctrl@59800000 {

			compatible = "socionext,uniphier-smpctrl";

			reg = <0x59801000 0x400>;

		};



		mioctrl@59810000 {

			compatible = "socionext,uniphier-ld4-mioctrl",

				     "simple-mfd", "syscon";

			reg = <0x59810000 0x800>;



			mio_clk: clock {

				compatible = "socionext,uniphier-ld4-mio-clock";

				#clock-cells = <1>;

			};



			mio_rst: reset {

				compatible = "socionext,uniphier-ld4-mio-reset";

				#reset-cells = <1>;

			};

		};



		perictrl@59820000 {

			compatible = "socionext,uniphier-ld4-perictrl",

				     "simple-mfd", "syscon";

			reg = <0x59820000 0x200>;



			peri_clk: clock {

				compatible = "socionext,uniphier-ld4-peri-clock";

				#clock-cells = <1>;

			};



			peri_rst: reset {

				compatible = "socionext,uniphier-ld4-peri-reset";

				#reset-cells = <1>;

			};

		};



		usb0: usb@5a800100 {

			compatible = "socionext,uniphier-ehci", "generic-ehci";

			status = "disabled";
@@ -142,7 +246,8 @@ 
			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_usb0>;

			clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;

		resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;

			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,

				 <&mio_rst 12>;

		};



		usb1: usb@5a810100 {
@@ -153,7 +258,8 @@ 
			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_usb1>;

			clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;

		resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;

			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,

				 <&mio_rst 13>;

		};



		usb2: usb@5a820100 {
@@ -164,44 +270,58 @@ 
			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_usb2>;

			clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;

		resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>;

			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,

				 <&mio_rst 14>;

		};



};

		soc-glue@5f800000 {

			compatible = "socionext,uniphier-ld4-soc-glue",

				     "simple-mfd", "syscon";

			reg = <0x5f800000 0x2000>;



&refclk {

	clock-frequency = <24576000>;

};



&serial3 {

	interrupts = <0 29 4>;

			pinctrl: pinctrl {

				compatible = "socionext,uniphier-ld4-pinctrl";

			};



&mio_clk {

	compatible = "socionext,uniphier-ld4-mio-clock";

		};



&mio_rst {

	compatible = "socionext,uniphier-ld4-mio-reset";

	resets = <&sys_rst 7>;

		timer@60000200 {

			compatible = "arm,cortex-a9-global-timer";

			reg = <0x60000200 0x20>;

			interrupts = <1 11 0x104>;

			clocks = <&arm_timer_clk>;

		};



&peri_clk {

	compatible = "socionext,uniphier-ld4-peri-clock";

		timer@60000600 {

			compatible = "arm,cortex-a9-twd-timer";

			reg = <0x60000600 0x20>;

			interrupts = <1 13 0x104>;

			clocks = <&arm_timer_clk>;

		};



&peri_rst {

	compatible = "socionext,uniphier-ld4-peri-reset";

		intc: interrupt-controller@60001000 {

			compatible = "arm,cortex-a9-gic";

			reg = <0x60001000 0x1000>,

			      <0x60000100 0x100>;

			#interrupt-cells = <3>;

			interrupt-controller;

		};



&pinctrl {

	compatible = "socionext,uniphier-ld4-pinctrl";

};

		sysctrl@61840000 {

			compatible = "socionext,uniphier-ld4-sysctrl",

				     "simple-mfd", "syscon";

			reg = <0x61840000 0x10000>;



&sys_clk {

			sys_clk: clock {

				compatible = "socionext,uniphier-ld4-clock";

				#clock-cells = <1>;

			};



&sys_rst {

			sys_rst: reset {

				compatible = "socionext,uniphier-ld4-reset";

				#reset-cells = <1>;

			};

		};

	};

};



/include/ "uniphier-pinctrl.dtsi"

arch/arm/boot/dts/uniphier-pro4.dtsi

+251 −127
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ 
 *     OTHER DEALINGS IN THE SOFTWARE.

 */



/include/ "uniphier-common32.dtsi"

/include/ "skeleton.dtsi"



/ {

	compatible = "socionext,uniphier-pro4";
@@ -69,19 +69,36 @@ 
		};

	};



	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	clocks {

		refclk: ref {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <25000000>;

		};



		arm_timer_clk: arm_timer_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <50000000>;

		};

	};

};



&soc {

	soc {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		interrupt-parent = <&intc>;



		l2: l2-cache@500c0000 {

			compatible = "socionext,uniphier-system-cache";

		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;

			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,

			      <0x506c0000 0x400>;

			interrupts = <0 174 4>, <0 175 4>;

			cache-unified;

			cache-size = <(768 * 1024)>;
@@ -90,6 +107,46 @@ 
			cache-level = <2>;

		};



		serial0: serial@54006800 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006800 0x40>;

			interrupts = <0 33 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart0>;

			clocks = <&peri_clk 0>;

		};



		serial1: serial@54006900 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006900 0x40>;

			interrupts = <0 35 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart1>;

			clocks = <&peri_clk 1>;

		};



		serial2: serial@54006a00 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006a00 0x40>;

			interrupts = <0 37 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart2>;

			clocks = <&peri_clk 2>;

		};



		serial3: serial@54006b00 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006b00 0x40>;

			interrupts = <0 177 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart3>;

			clocks = <&peri_clk 3>;

		};



		i2c0: i2c@58780000 {

			compatible = "socionext,uniphier-fi2c";

			status = "disabled";
@@ -166,6 +223,53 @@ 
			clock-frequency = <400000>;

		};



		system_bus: system-bus@58c00000 {

			compatible = "socionext,uniphier-system-bus";

			status = "disabled";

			reg = <0x58c00000 0x400>;

			#address-cells = <2>;

			#size-cells = <1>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_system_bus>;

		};



		smpctrl@59800000 {

			compatible = "socionext,uniphier-smpctrl";

			reg = <0x59801000 0x400>;

		};



		mioctrl@59810000 {

			compatible = "socionext,uniphier-pro4-mioctrl",

				     "simple-mfd", "syscon";

			reg = <0x59810000 0x800>;



			mio_clk: clock {

				compatible = "socionext,uniphier-pro4-mio-clock";

				#clock-cells = <1>;

			};



			mio_rst: reset {

				compatible = "socionext,uniphier-pro4-mio-reset";

				#reset-cells = <1>;

			};

		};



		perictrl@59820000 {

			compatible = "socionext,uniphier-pro4-perictrl",

				     "simple-mfd", "syscon";

			reg = <0x59820000 0x200>;



			peri_clk: clock {

				compatible = "socionext,uniphier-pro4-peri-clock";

				#clock-cells = <1>;

			};



			peri_rst: reset {

				compatible = "socionext,uniphier-pro4-peri-reset";

				#reset-cells = <1>;

			};

		};



		usb2: usb@5a800100 {

			compatible = "socionext,uniphier-ehci", "generic-ehci";

			status = "disabled";
@@ -174,7 +278,8 @@ 
			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_usb2>;

			clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;

		resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;

			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,

				 <&mio_rst 12>;

		};



		usb3: usb@5a810100 {
@@ -185,39 +290,58 @@ 
			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_usb3>;

			clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;

		resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;

	};

			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,

				 <&mio_rst 13>;

		};



&refclk {

	clock-frequency = <25000000>;

};

		soc-glue@5f800000 {

			compatible = "socionext,uniphier-pro4-soc-glue",

				     "simple-mfd", "syscon";

			reg = <0x5f800000 0x2000>;



&mio_clk {

	compatible = "socionext,uniphier-pro4-mio-clock";

			pinctrl: pinctrl {

				compatible = "socionext,uniphier-pro4-pinctrl";

			};



&mio_rst {

	compatible = "socionext,uniphier-pro4-mio-reset";

	resets = <&sys_rst 7>;

		};



&peri_clk {

	compatible = "socionext,uniphier-pro4-peri-clock";

		timer@60000200 {

			compatible = "arm,cortex-a9-global-timer";

			reg = <0x60000200 0x20>;

			interrupts = <1 11 0x304>;

			clocks = <&arm_timer_clk>;

		};



&peri_rst {

	compatible = "socionext,uniphier-pro4-peri-reset";

		timer@60000600 {

			compatible = "arm,cortex-a9-twd-timer";

			reg = <0x60000600 0x20>;

			interrupts = <1 13 0x304>;

			clocks = <&arm_timer_clk>;

		};



&pinctrl {

	compatible = "socionext,uniphier-pro4-pinctrl";

		intc: interrupt-controller@60001000 {

			compatible = "arm,cortex-a9-gic";

			reg = <0x60001000 0x1000>,

			      <0x60000100 0x100>;

			#interrupt-cells = <3>;

			interrupt-controller;

		};



&sys_clk {

		sysctrl@61840000 {

			compatible = "socionext,uniphier-pro4-sysctrl",

				     "simple-mfd", "syscon";

			reg = <0x61840000 0x10000>;



			sys_clk: clock {

				compatible = "socionext,uniphier-pro4-clock";

				#clock-cells = <1>;

			};



&sys_rst {

			sys_rst: reset {

				compatible = "socionext,uniphier-pro4-reset";

				#reset-cells = <1>;

			};

		};

	};

};



/include/ "uniphier-pinctrl.dtsi"

arch/arm/boot/dts/uniphier-pro5.dtsi

+315 −117
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ 
 *     OTHER DEALINGS IN THE SOFTWARE.

 */



/include/ "uniphier-common32.dtsi"

/include/ "skeleton.dtsi"



/ {

	compatible = "socionext,uniphier-pro5";
@@ -56,32 +56,123 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0>;

			clocks = <&sys_clk 32>;

			enable-method = "psci";

			next-level-cache = <&l2>;

			operating-points-v2 = <&cpu_opp>;

		};



		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <1>;

			clocks = <&sys_clk 32>;

			enable-method = "psci";

			next-level-cache = <&l2>;

			operating-points-v2 = <&cpu_opp>;

		};

	};



	cpu_opp: opp_table {

		compatible = "operating-points-v2";

		opp-shared;



		opp@100000000 {

			opp-hz = /bits/ 64 <100000000>;

			clock-latency-ns = <300>;

		};

		opp@116667000 {

			opp-hz = /bits/ 64 <116667000>;

			clock-latency-ns = <300>;

		};

		opp@150000000 {

			opp-hz = /bits/ 64 <150000000>;

			clock-latency-ns = <300>;

		};

		opp@175000000 {

			opp-hz = /bits/ 64 <175000000>;

			clock-latency-ns = <300>;

		};

		opp@200000000 {

			opp-hz = /bits/ 64 <200000000>;

			clock-latency-ns = <300>;

		};

		opp@233334000 {

			opp-hz = /bits/ 64 <233334000>;

			clock-latency-ns = <300>;

		};

		opp@300000000 {

			opp-hz = /bits/ 64 <300000000>;

			clock-latency-ns = <300>;

		};

		opp@350000000 {

			opp-hz = /bits/ 64 <350000000>;

			clock-latency-ns = <300>;

		};

		opp@400000000 {

			opp-hz = /bits/ 64 <400000000>;

			clock-latency-ns = <300>;

		};

		opp@466667000 {

			opp-hz = /bits/ 64 <466667000>;

			clock-latency-ns = <300>;

		};

		opp@600000000 {

			opp-hz = /bits/ 64 <600000000>;

			clock-latency-ns = <300>;

		};

		opp@700000000 {

			opp-hz = /bits/ 64 <700000000>;

			clock-latency-ns = <300>;

		};

		opp@800000000 {

			opp-hz = /bits/ 64 <800000000>;

			clock-latency-ns = <300>;

		};

		opp@933334000 {

			opp-hz = /bits/ 64 <933334000>;

			clock-latency-ns = <300>;

		};

		opp@1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			clock-latency-ns = <300>;

		};

		opp@1400000000 {

			opp-hz = /bits/ 64 <1400000000>;

			clock-latency-ns = <300>;

		};

	};



	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	clocks {

		refclk: ref {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <20000000>;

		};



		arm_timer_clk: arm_timer_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <50000000>;

		};

	};

};



&soc {

	soc {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		interrupt-parent = <&intc>;



		l2: l2-cache@500c0000 {

			compatible = "socionext,uniphier-system-cache";

		reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;

			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,

			      <0x506c0000 0x400>;

			interrupts = <0 190 4>, <0 191 4>;

			cache-unified;

			cache-size = <(2 * 1024 * 1024)>;
@@ -93,7 +184,8 @@ 


		l3: l3-cache@500c8000 {

			compatible = "socionext,uniphier-system-cache";

		reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;

			reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,

			      <0x506c8000 0x400>;

			interrupts = <0 174 4>, <0 175 4>;

			cache-unified;

			cache-size = <(2 * 1024 * 1024)>;
@@ -102,6 +194,46 @@ 
			cache-level = <3>;

		};



		serial0: serial@54006800 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006800 0x40>;

			interrupts = <0 33 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart0>;

			clocks = <&peri_clk 0>;

		};



		serial1: serial@54006900 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006900 0x40>;

			interrupts = <0 35 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart1>;

			clocks = <&peri_clk 1>;

		};



		serial2: serial@54006a00 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006a00 0x40>;

			interrupts = <0 37 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart2>;

			clocks = <&peri_clk 2>;

		};



		serial3: serial@54006b00 {

			compatible = "socionext,uniphier-uart";

			status = "disabled";

			reg = <0x54006b00 0x40>;

			interrupts = <0 177 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart3>;

			clocks = <&peri_clk 3>;

		};



		i2c0: i2c@58780000 {

			compatible = "socionext,uniphier-fi2c";

			status = "disabled";
@@ -177,36 +309,102 @@ 
			clocks = <&peri_clk 10>;

			clock-frequency = <400000>;

		};



		system_bus: system-bus@58c00000 {

			compatible = "socionext,uniphier-system-bus";

			status = "disabled";

			reg = <0x58c00000 0x400>;

			#address-cells = <2>;

			#size-cells = <1>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_system_bus>;

		};



&refclk {

	clock-frequency = <20000000>;

		smpctrl@59800000 {

			compatible = "socionext,uniphier-smpctrl";

			reg = <0x59801000 0x400>;

		};



&mio_clk {

		sdctrl@59810000 {

			compatible = "socionext,uniphier-pro5-sdctrl",

				     "simple-mfd", "syscon";

			reg = <0x59810000 0x800>;



			sd_clk: clock {

				compatible = "socionext,uniphier-pro5-sd-clock";

				#clock-cells = <1>;

			};



&mio_rst {

			sd_rst: reset {

				compatible = "socionext,uniphier-pro5-sd-reset";

				#reset-cells = <1>;

			};

		};



		perictrl@59820000 {

			compatible = "socionext,uniphier-pro5-perictrl",

				     "simple-mfd", "syscon";

			reg = <0x59820000 0x200>;



&peri_clk {

			peri_clk: clock {

				compatible = "socionext,uniphier-pro5-peri-clock";

				#clock-cells = <1>;

			};



&peri_rst {

			peri_rst: reset {

				compatible = "socionext,uniphier-pro5-peri-reset";

				#reset-cells = <1>;

			};

		};



		soc-glue@5f800000 {

			compatible = "socionext,uniphier-pro5-soc-glue",

				     "simple-mfd", "syscon";

			reg = <0x5f800000 0x2000>;



&pinctrl {

			pinctrl: pinctrl {

				compatible = "socionext,uniphier-pro5-pinctrl";

			};

		};



		timer@60000200 {

			compatible = "arm,cortex-a9-global-timer";

			reg = <0x60000200 0x20>;

			interrupts = <1 11 0x304>;

			clocks = <&arm_timer_clk>;

		};



		timer@60000600 {

			compatible = "arm,cortex-a9-twd-timer";

			reg = <0x60000600 0x20>;

			interrupts = <1 13 0x304>;

			clocks = <&arm_timer_clk>;

		};



		intc: interrupt-controller@60001000 {

			compatible = "arm,cortex-a9-gic";

			reg = <0x60001000 0x1000>,

			      <0x60000100 0x100>;

			#interrupt-cells = <3>;

			interrupt-controller;

		};



		sysctrl@61840000 {

			compatible = "socionext,uniphier-pro5-sysctrl",

				     "simple-mfd", "syscon";

			reg = <0x61840000 0x10000>;



&sys_clk {

			sys_clk: clock {

				compatible = "socionext,uniphier-pro5-clock";

				#clock-cells = <1>;

			};



&sys_rst {

			sys_rst: reset {

				compatible = "socionext,uniphier-pro5-reset";

				#reset-cells = <1>;

			};

		};

	};

};



/include/ "uniphier-pinctrl.dtsi"

arch/arm/boot/dts/uniphier-pxs2.dtsi

+284 −115

File changed.

Preview size limit exceeded, changes collapsed.