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Commit a84ec521 authored by zhuo's avatar zhuo
Browse files

msm: camera: csiphy: Add csiphy header file delta 



This change add csiphy header file delta from camera-kernel.3.1
to camera-kernel.4.0.

CRs-Fixed: 2998514
Change-Id: I802b25fe3939edb5294536f2e26307105c6667f0
Signed-off-by: default avatarzhuo <zhuo@codeaurora.org>
parent 78f83a40

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c

+1 −1
Original line number Diff line number Diff line
@@ -481,7 +481,7 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, 
		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;

		csiphy_dev->is_divisor_32_comp = false;

		csiphy_dev->clk_lane = 0;

		csiphy_dev->ctrl_reg->data_rates_settings_table = NULL;

		csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_2_0;

	} else if (of_device_is_compatible(soc_info->dev->of_node,

		"qcom,csiphy-v2.1.0")) {

		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_1_0_reg;

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h

+58 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.

 */



#ifndef _CAM_CSIPHY_2_0_HWREG_H_
@@ -291,4 +291,61 @@ struct csiphy_reg_t csiphy_3ph_v2_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
	},

};



struct data_rate_settings_t data_rate_delta_table_2_0 = {

	.num_data_rate_settings = 2,

	.data_rate_settings = {

		{

			/* (2 * 10**9 * 2.28) rounded value*/

			.bandwidth = 4560000000,

			.data_rate_reg_array_size = 1,

			.per_lane_info = {

				{

					.lane_identifier = CPHY_LANE_0,

					.csiphy_data_rate_regs = {

						{0x164, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},

					},

				},

				{

					.lane_identifier = CPHY_LANE_1,

					.csiphy_data_rate_regs = {

						{0x364, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},

					},

				},

				{

					.lane_identifier = CPHY_LANE_2,

					.csiphy_data_rate_regs = {

						{0x564, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},

					},

				},

			},

		},

		{

			/* (2.5 * 10**9 * 2.28) rounded value*/

			.bandwidth = 5700000000,

			.data_rate_reg_array_size = 1,

			.per_lane_info = {

				{

					.lane_identifier = CPHY_LANE_0,

					.csiphy_data_rate_regs = {

						{0x164, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},

					},

				},

				{

					.lane_identifier = CPHY_LANE_1,

					.csiphy_data_rate_regs = {

						{0x364, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},

					},

				},

				{

					.lane_identifier = CPHY_LANE_2,

					.csiphy_data_rate_regs = {

						{0x564, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},

					},

				},

			},

		},

	},



};



#endif /* _CAM_CSIPHY_2_0_HWREG_H_ */