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Commit a7f014f2 authored by Eric Anholt's avatar Eric Anholt Committed by Dave Airlie
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drm/i915: Respect GM965/GM45 bit-17-instead-of-bit-11 option for swizzling. 



This fixes readpixels and buffer corruption when swapped out and in by
disabling tiling on them.

Now that we know that the bit 17 mode isn't just a mistake of older chipsets,
we'll need to work on a clever fix so that we can get the performance of
tiling on these chipsets, but that will require intrusive changes targeted
at the next kernel release, not this one.

Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent feaf3848

drivers/gpu/drm/i915/i915_gem_tiling.c

+4 −3
Original line number Diff line number Diff line
@@ -119,9 +119,10 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) 
			    dcc & DCC_CHANNEL_XOR_DISABLE) {

				swizzle_x = I915_BIT_6_SWIZZLE_9_10;

				swizzle_y = I915_BIT_6_SWIZZLE_9;

			} else if (IS_I965GM(dev) || IS_GM45(dev)) {

				/* GM965 only does bit 11-based channel

				 * randomization

			} else if ((IS_I965GM(dev) || IS_GM45(dev)) &&

				   (dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {

				/* GM965/GM45 does either bit 11 or bit 17

				 * swizzling.

				 */

				swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;

				swizzle_y = I915_BIT_6_SWIZZLE_9_11;

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -522,6 +522,7 @@ 
#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)

#define DCC_ADDRESSING_MODE_MASK			(3 << 0)

#define DCC_CHANNEL_XOR_DISABLE				(1 << 10)

#define DCC_CHANNEL_XOR_BIT_17				(1 << 9)



/** 965 MCH register controlling DRAM channel configuration */

#define C0DRB3			0x10206