Commit a681e6d6 authored Mar 07, 2017 by Geert Uytterhoeven Committed by Simon Horman Mar 10, 2017

arm64: dts: r8a7796: Add CA53 L2 cache-controller node



Add a device node for the Cortex-A53 L2 cache-controller.

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).

Extracted from a patch by Takeshi Kihara in the BSP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

parent 9fccf4d6

arch/arm64/boot/dts/renesas/r8a7796.dtsi

+7 −0

Original line number	Diff line number	Diff line
		@@ -61,6 +61,13 @@
		cache-unified;
		cache-level = <2>;
		};

		L2_CA53: cache-controller-1 {
		compatible = "cache";
		power-domains = <&sysc R8A7796_PD_CA53_SCU>;
		cache-unified;
		cache-level = <2>;
		};
		};

		extal_clk: extal {