clk: ti: Convert to clk_hw based provider APIs (a53ad8ef) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/clk/ti/autoidle.c

+4 −4

Original line number	Original line	Diff line number	Diff line
	@@ -169,21 +169,21 @@ int __init of_ti_clk_autoidle_setup(struct device_node *node)

	/**		/**
	* omap2_init_clk_hw_omap_clocks - initialize an OMAP clock		* omap2_init_clk_hw_omap_clocks - initialize an OMAP clock
	* @clk: struct clk * to initialize		* @hw: struct clk_hw * to initialize
	*		*
	* Add an OMAP clock @clk to the internal list of OMAP clocks. Used		* Add an OMAP clock @clk to the internal list of OMAP clocks. Used
	* temporarily for autoidle handling, until this support can be		* temporarily for autoidle handling, until this support can be
	* integrated into the common clock framework code in some way. No		* integrated into the common clock framework code in some way. No
	* return value.		* return value.
	*/		*/
	void omap2_init_clk_hw_omap_clocks(struct clk *clk)		void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw)
	{		{
	struct clk_hw_omap *c;		struct clk_hw_omap *c;

	if (__clk_get_flags(clk) & CLK_IS_BASIC)		if (clk_hw_get_flags(hw) & CLK_IS_BASIC)
	return;		return;

	c = to_clk_hw_omap(__clk_get_hw(clk));		c = to_clk_hw_omap(hw);
	list_add(&c->node, &clk_hw_omap_clocks);		list_add(&c->node, &clk_hw_omap_clocks);
	}		}

drivers/clk/ti/clkt_dpll.c

+6 −5

Original line number	Original line	Diff line number	Diff line
	@@ -16,6 +16,7 @@

	#include <linux/kernel.h>		#include <linux/kernel.h>
	#include <linux/errno.h>		#include <linux/errno.h>
			#include <linux/clk.h>
	#include <linux/clk-provider.h>		#include <linux/clk-provider.h>
	#include <linux/io.h>		#include <linux/io.h>
	#include <linux/clk/ti.h>		#include <linux/clk/ti.h>
	@@ -75,7 +76,7 @@ static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)
	dd = clk->dpll_data;		dd = clk->dpll_data;

	/* DPLL divider must result in a valid jitter correction val */		/* DPLL divider must result in a valid jitter correction val */
	fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;		fint = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)) / n;

	if (dd->flags & DPLL_J_TYPE) {		if (dd->flags & DPLL_J_TYPE) {
	fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;		fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
	@@ -253,7 +254,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
	v >>= __ffs(dd->enable_mask);		v >>= __ffs(dd->enable_mask);

	if (_omap2_dpll_is_in_bypass(v))		if (_omap2_dpll_is_in_bypass(v))
	return __clk_get_rate(dd->clk_bypass);		return clk_get_rate(dd->clk_bypass);

	v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg);		v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg);
	dpll_mult = v & dd->mult_mask;		dpll_mult = v & dd->mult_mask;
	@@ -261,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
	dpll_div = v & dd->div1_mask;		dpll_div = v & dd->div1_mask;
	dpll_div >>= __ffs(dd->div1_mask);		dpll_div >>= __ffs(dd->div1_mask);

	dpll_clk = (long long)__clk_get_rate(dd->clk_ref) * dpll_mult;		dpll_clk = (long long)clk_get_rate(dd->clk_ref) * dpll_mult;
	do_div(dpll_clk, dpll_div + 1);		do_div(dpll_clk, dpll_div + 1);

	return dpll_clk;		return dpll_clk;
	@@ -300,8 +301,8 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,

	dd = clk->dpll_data;		dd = clk->dpll_data;

	ref_rate = __clk_get_rate(dd->clk_ref);		ref_rate = clk_get_rate(dd->clk_ref);
	clk_name = __clk_get_name(hw->clk);		clk_name = clk_hw_get_name(hw);
	pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",		pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
	clk_name, target_rate);		clk_name, target_rate);

drivers/clk/ti/clock.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -204,7 +204,7 @@ int ti_clk_retry_init(struct device_node node, struct clk_hw hw,
	ti_of_clk_init_cb_t func);		ti_of_clk_init_cb_t func);
	int ti_clk_add_component(struct device_node node, struct clk_hw hw, int type);		int ti_clk_add_component(struct device_node node, struct clk_hw hw, int type);

	void omap2_init_clk_hw_omap_clocks(struct clk *clk);		void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw);
	int of_ti_clk_autoidle_setup(struct device_node *node);		int of_ti_clk_autoidle_setup(struct device_node *node);
	void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);		void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);

drivers/clk/ti/divider.c

+3 −3

Original line number	Original line	Diff line number	Diff line
	@@ -109,7 +109,7 @@ static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
	if (!div) {		if (!div) {
	WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
	"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",		"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
	__clk_get_name(hw->clk));		clk_hw_get_name(hw));
	return parent_rate;		return parent_rate;
	}		}

	@@ -181,7 +181,7 @@ static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
	*best_parent_rate = parent_rate_saved;		*best_parent_rate = parent_rate_saved;
	return i;		return i;
	}		}
	parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),		parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
	MULT_ROUND_UP(rate, i));		MULT_ROUND_UP(rate, i));
	now = DIV_ROUND_UP(parent_rate, i);		now = DIV_ROUND_UP(parent_rate, i);
	if (now <= rate && now > best) {		if (now <= rate && now > best) {
	@@ -194,7 +194,7 @@ static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
	if (!bestdiv) {		if (!bestdiv) {
	bestdiv = _get_maxdiv(divider);		bestdiv = _get_maxdiv(divider);
	*best_parent_rate =		*best_parent_rate =
	__clk_round_rate(__clk_get_parent(hw->clk), 1);		clk_hw_round_rate(clk_hw_get_parent(hw), 1);
	}		}

	return bestdiv;		return bestdiv;

drivers/clk/ti/dpll3xxx.c

+14 −17

Original line number	Original line	Diff line number	Diff line
	@@ -69,7 +69,7 @@ static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
	const char *clk_name;		const char *clk_name;

	dd = clk->dpll_data;		dd = clk->dpll_data;
	clk_name = __clk_get_name(clk->hw.clk);		clk_name = clk_hw_get_name(&clk->hw);

	state <<= __ffs(dd->idlest_mask);		state <<= __ffs(dd->idlest_mask);

	@@ -98,7 +98,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
	unsigned long fint;		unsigned long fint;
	u16 f = 0;		u16 f = 0;

	fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;		fint = clk_get_rate(clk->dpll_data->clk_ref) / n;

	pr_debug("clock: fint is %lu\n", fint);		pr_debug("clock: fint is %lu\n", fint);

	@@ -145,7 +145,7 @@ static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
	u8 state = 1;		u8 state = 1;
	int r = 0;		int r = 0;

	pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk));		pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw));

	dd = clk->dpll_data;		dd = clk->dpll_data;
	state <<= __ffs(dd->idlest_mask);		state <<= __ffs(dd->idlest_mask);
	@@ -193,7 +193,7 @@ static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
	return -EINVAL;		return -EINVAL;

	pr_debug("clock: configuring DPLL %s for low-power bypass\n",		pr_debug("clock: configuring DPLL %s for low-power bypass\n",
	__clk_get_name(clk->hw.clk));		clk_hw_get_name(&clk->hw));

	ai = omap3_dpll_autoidle_read(clk);		ai = omap3_dpll_autoidle_read(clk);

	@@ -223,7 +223,7 @@ static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
	if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))		if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
	return -EINVAL;		return -EINVAL;

	pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk));		pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw));

	ai = omap3_dpll_autoidle_read(clk);		ai = omap3_dpll_autoidle_read(clk);

	@@ -251,7 +251,7 @@ static void _lookup_dco(struct clk_hw_omap clk, u8 dco, u16 m, u8 n)
	{		{
	unsigned long fint, clkinp; /* watch out for overflow */		unsigned long fint, clkinp; /* watch out for overflow */

	clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));		clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
	fint = (clkinp / n) * m;		fint = (clkinp / n) * m;

	if (fint < 1000000000)		if (fint < 1000000000)
	@@ -277,7 +277,7 @@ static void _lookup_sddiv(struct clk_hw_omap clk, u8 sd_div, u16 m, u8 n)
	unsigned long clkinp, sd; /* watch out for overflow */		unsigned long clkinp, sd; /* watch out for overflow */
	int mod1, mod2;		int mod1, mod2;

	clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));		clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));

	/*		/*
	* target sigma-delta to near 250MHz		* target sigma-delta to near 250MHz
	@@ -429,15 +429,15 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw)
	if (r) {		if (r) {
	WARN(1,		WARN(1,
	"%s: could not enable %s's clockdomain %s: %d\n",		"%s: could not enable %s's clockdomain %s: %d\n",
	__func__, __clk_get_name(hw->clk),		__func__, clk_hw_get_name(hw),
	clk->clkdm_name, r);		clk->clkdm_name, r);
	return r;		return r;
	}		}
	}		}

	parent = __clk_get_hw(__clk_get_parent(hw->clk));		parent = clk_hw_get_parent(hw);

	if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {		if (clk_hw_get_rate(hw) == clk_get_rate(dd->clk_bypass)) {
	WARN_ON(parent != __clk_get_hw(dd->clk_bypass));		WARN_ON(parent != __clk_get_hw(dd->clk_bypass));
	r = _omap3_noncore_dpll_bypass(clk);		r = _omap3_noncore_dpll_bypass(clk);
	} else {		} else {
	@@ -489,7 +489,7 @@ int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
	if (!dd)		if (!dd)
	return -EINVAL;		return -EINVAL;

	if (__clk_get_rate(dd->clk_bypass) == req->rate &&		if (clk_get_rate(dd->clk_bypass) == req->rate &&
	(dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {		(dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
	req->best_parent_hw = __clk_get_hw(dd->clk_bypass);		req->best_parent_hw = __clk_get_hw(dd->clk_bypass);
	} else {		} else {
	@@ -553,8 +553,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
	if (!dd)		if (!dd)
	return -EINVAL;		return -EINVAL;

	if (__clk_get_hw(__clk_get_parent(hw->clk)) !=		if (clk_hw_get_parent(hw) != __clk_get_hw(dd->clk_ref))
	__clk_get_hw(dd->clk_ref))
	return -EINVAL;		return -EINVAL;

	if (dd->last_rounded_rate == 0)		if (dd->last_rounded_rate == 0)
	@@ -567,7 +566,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
	}		}

	pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__,		pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__,
	__clk_get_name(hw->clk), rate);		clk_hw_get_name(hw), rate);

	ret = omap3_noncore_dpll_program(clk, freqsel);		ret = omap3_noncore_dpll_program(clk, freqsel);

	@@ -704,13 +703,11 @@ static void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
	static struct clk_hw_omap omap3_find_clkoutx2_dpll(struct clk_hw hw)		static struct clk_hw_omap omap3_find_clkoutx2_dpll(struct clk_hw hw)
	{		{
	struct clk_hw_omap *pclk = NULL;		struct clk_hw_omap *pclk = NULL;
	struct clk *parent;

	/* Walk up the parents of clk, looking for a DPLL */		/* Walk up the parents of clk, looking for a DPLL */
	do {		do {
	do {		do {
	parent = __clk_get_parent(hw->clk);		hw = clk_hw_get_parent(hw);
	hw = __clk_get_hw(parent);
	} while (hw && (clk_hw_get_flags(hw) & CLK_IS_BASIC));		} while (hw && (clk_hw_get_flags(hw) & CLK_IS_BASIC));
	if (!hw)		if (!hw)
	break;		break;