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Commit a5073d60 authored by Yixian Liu's avatar Yixian Liu Committed by Jason Gunthorpe
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RDMA/hns: Add eq support of hip08 



This patch adds eq support for hip08. The eq table can
be multi-hop addressed.

Signed-off-by: default avatarYixian Liu <liuyixian@huawei.com>
Reviewed-by: default avatarLijun Ou <oulijun@huawei.com>
Reviewed-by: default avatarWei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@mellanox.com>
parent b16f8188

drivers/infiniband/hw/hns/hns_roce_cmd.h

+10 −0
Original line number Original line Diff line number Diff line
@@ -88,6 +88,16 @@ enum { 
	HNS_ROCE_CMD_DESTROY_SRQC_BT0	= 0x38,

	HNS_ROCE_CMD_DESTROY_SRQC_BT0	= 0x38,

	HNS_ROCE_CMD_DESTROY_SRQC_BT1	= 0x39,

	HNS_ROCE_CMD_DESTROY_SRQC_BT1	= 0x39,

	HNS_ROCE_CMD_DESTROY_SRQC_BT2	= 0x3a,

	HNS_ROCE_CMD_DESTROY_SRQC_BT2	= 0x3a,



	/* EQC commands */

	HNS_ROCE_CMD_CREATE_AEQC	= 0x80,

	HNS_ROCE_CMD_MODIFY_AEQC	= 0x81,

	HNS_ROCE_CMD_QUERY_AEQC		= 0x82,

	HNS_ROCE_CMD_DESTROY_AEQC	= 0x83,

	HNS_ROCE_CMD_CREATE_CEQC	= 0x90,

	HNS_ROCE_CMD_MODIFY_CEQC	= 0x91,

	HNS_ROCE_CMD_QUERY_CEQC		= 0x92,

	HNS_ROCE_CMD_DESTROY_CEQC	= 0x93,

};

};





enum {

enum {

drivers/infiniband/hw/hns/hns_roce_common.h

+11 −0
Original line number Original line Diff line number Diff line
@@ -376,6 +376,12 @@ 
#define ROCEE_RX_CMQ_TAIL_REG			0x07024

#define ROCEE_RX_CMQ_TAIL_REG			0x07024

#define ROCEE_RX_CMQ_HEAD_REG			0x07028

#define ROCEE_RX_CMQ_HEAD_REG			0x07028





#define ROCEE_VF_MB_CFG0_REG			0x40

#define ROCEE_VF_MB_STATUS_REG			0x58



#define ROCEE_VF_EQ_DB_CFG0_REG			0x238

#define ROCEE_VF_EQ_DB_CFG1_REG			0x23C



#define ROCEE_VF_SMAC_CFG0_REG			0x12000

#define ROCEE_VF_SMAC_CFG0_REG			0x12000

#define ROCEE_VF_SMAC_CFG1_REG			0x12004

#define ROCEE_VF_SMAC_CFG1_REG			0x12004
@@ -385,4 +391,9 @@ 
#define ROCEE_VF_SGID_CFG3_REG			0x1000c

#define ROCEE_VF_SGID_CFG3_REG			0x1000c

#define ROCEE_VF_SGID_CFG4_REG			0x10010

#define ROCEE_VF_SGID_CFG4_REG			0x10010





#define ROCEE_VF_ABN_INT_CFG_REG		0x13000

#define ROCEE_VF_ABN_INT_ST_REG			0x13004

#define ROCEE_VF_ABN_INT_EN_REG			0x13008

#define ROCEE_VF_EVENT_INT_EN_REG		0x1300c



#endif /* _HNS_ROCE_COMMON_H */
 
#endif /* _HNS_ROCE_COMMON_H */

drivers/infiniband/hw/hns/hns_roce_device.h

+25 −1
Original line number Original line Diff line number Diff line
@@ -134,6 +134,7 @@ enum hns_roce_event { 
	HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,

	HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,

	HNS_ROCE_EVENT_TYPE_MB                        = 0x13,

	HNS_ROCE_EVENT_TYPE_MB                        = 0x13,

	HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW              = 0x14,

	HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW              = 0x14,

	HNS_ROCE_EVENT_TYPE_FLR			      = 0x15,

};

};





/* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */

/* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
@@ -541,6 +542,26 @@ struct hns_roce_eq { 
	int				log_page_size;

	int				log_page_size;

	int				cons_index;

	int				cons_index;

	struct hns_roce_buf_list	*buf_list;

	struct hns_roce_buf_list	*buf_list;

	int				over_ignore;

	int				coalesce;

	int				arm_st;

	u64				eqe_ba;

	int				eqe_ba_pg_sz;

	int				eqe_buf_pg_sz;

	int				hop_num;

	u64				*bt_l0;	/* Base address table for L0 */

	u64				**bt_l1; /* Base address table for L1 */

	u64				**buf;

	dma_addr_t			l0_dma;

	dma_addr_t			*l1_dma;

	dma_addr_t			*buf_dma;

	u32				l0_last_num; /* L0 last chunk num */

	u32				l1_last_num; /* L1 last chunk num */

	int				eq_max_cnt;

	int				eq_period;

	int				shift;

	dma_addr_t			cur_eqe_ba;

	dma_addr_t			nxt_eqe_ba;

};

};





struct hns_roce_eq_table {

struct hns_roce_eq_table {
@@ -571,7 +592,7 @@ struct hns_roce_caps { 
	u32		min_wqes;

	u32		min_wqes;

	int		reserved_cqs;

	int		reserved_cqs;

	int		num_aeq_vectors;	/* 1 */

	int		num_aeq_vectors;	/* 1 */

	int		num_comp_vectors;	/* 32 ceq */

	int		num_comp_vectors;

	int		num_other_vectors;

	int		num_other_vectors;

	int		num_mtpts;

	int		num_mtpts;

	u32		num_mtt_segs;

	u32		num_mtt_segs;
@@ -617,6 +638,9 @@ struct hns_roce_caps { 
	u32		cqe_ba_pg_sz;

	u32		cqe_ba_pg_sz;

	u32		cqe_buf_pg_sz;

	u32		cqe_buf_pg_sz;

	u32		cqe_hop_num;

	u32		cqe_hop_num;

	u32		eqe_ba_pg_sz;

	u32		eqe_buf_pg_sz;

	u32		eqe_hop_num;

	u32		chunk_sz;	/* chunk size in non multihop mode*/

	u32		chunk_sz;	/* chunk size in non multihop mode*/

	u64		flags;

	u64		flags;

};

};

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+1173 −4

File changed.

Preview size limit exceeded, changes collapsed.

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+189 −3
Original line number Original line Diff line number Diff line
@@ -53,6 +53,10 @@ 
#define HNS_ROCE_V2_MAX_SQ_INLINE		0x20

#define HNS_ROCE_V2_MAX_SQ_INLINE		0x20

#define HNS_ROCE_V2_UAR_NUM			256

#define HNS_ROCE_V2_UAR_NUM			256

#define HNS_ROCE_V2_PHY_UAR_NUM			1

#define HNS_ROCE_V2_PHY_UAR_NUM			1

#define HNS_ROCE_V2_MAX_IRQ_NUM			65

#define HNS_ROCE_V2_COMP_VEC_NUM		63

#define HNS_ROCE_V2_AEQE_VEC_NUM		1

#define HNS_ROCE_V2_ABNORMAL_VEC_NUM		1

#define HNS_ROCE_V2_MAX_MTPT_NUM		0x8000

#define HNS_ROCE_V2_MAX_MTPT_NUM		0x8000

#define HNS_ROCE_V2_MAX_MTT_SEGS		0x1000000

#define HNS_ROCE_V2_MAX_MTT_SEGS		0x1000000

#define HNS_ROCE_V2_MAX_CQE_SEGS		0x1000000

#define HNS_ROCE_V2_MAX_CQE_SEGS		0x1000000
@@ -78,6 +82,8 @@ 
#define HNS_ROCE_MTT_HOP_NUM			1

#define HNS_ROCE_MTT_HOP_NUM			1

#define HNS_ROCE_CQE_HOP_NUM			1

#define HNS_ROCE_CQE_HOP_NUM			1

#define HNS_ROCE_PBL_HOP_NUM			2

#define HNS_ROCE_PBL_HOP_NUM			2

#define HNS_ROCE_EQE_HOP_NUM			2



#define HNS_ROCE_V2_GID_INDEX_NUM		256

#define HNS_ROCE_V2_GID_INDEX_NUM		256





#define HNS_ROCE_V2_TABLE_CHUNK_SIZE		(1 << 18)

#define HNS_ROCE_V2_TABLE_CHUNK_SIZE		(1 << 18)
@@ -105,6 +111,12 @@ 
	(step_idx == 1 && hop_num == 1) || \

	(step_idx == 1 && hop_num == 1) || \

	(step_idx == 2 && hop_num == 2))

	(step_idx == 2 && hop_num == 2))





enum {

	NO_ARMED = 0x0,

	REG_NXT_CEQE = 0x2,

	REG_NXT_SE_CEQE = 0x3

};



#define V2_CQ_DB_REQ_NOT_SOL			0

#define V2_CQ_DB_REQ_NOT_SOL			0

#define V2_CQ_DB_REQ_NOT			1

#define V2_CQ_DB_REQ_NOT			1
@@ -229,6 +241,9 @@ struct hns_roce_v2_cq_context { 
	u32	cqe_report_timer;

	u32	cqe_report_timer;

	u32	byte_64_se_cqe_idx;

	u32	byte_64_se_cqe_idx;

};

};

#define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0

#define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL	0x0



#define	V2_CQC_BYTE_4_CQ_ST_S 0

#define	V2_CQC_BYTE_4_CQ_ST_S 0

#define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0)

#define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0)
@@ -1129,9 +1144,6 @@ struct hns_roce_cmq_desc { 
	u32 data[6];

	u32 data[6];

};

};





#define ROCEE_VF_MB_CFG0_REG		0x40

#define ROCEE_VF_MB_STATUS_REG		0x58



#define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS	10000

#define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS	10000





#define HNS_ROCE_HW_RUN_BIT_SHIFT	31

#define HNS_ROCE_HW_RUN_BIT_SHIFT	31
@@ -1174,4 +1186,178 @@ struct hns_roce_v2_priv { 
	struct hns_roce_v2_cmq cmq;

	struct hns_roce_v2_cmq cmq;

};

};





struct hns_roce_eq_context {

	u32	byte_4;

	u32	byte_8;

	u32	byte_12;

	u32	eqe_report_timer;

	u32	eqe_ba0;

	u32	eqe_ba1;

	u32	byte_28;

	u32	byte_32;

	u32	byte_36;

	u32	nxt_eqe_ba0;

	u32	nxt_eqe_ba1;

	u32	rsv[5];

};



#define HNS_ROCE_AEQ_DEFAULT_BURST_NUM	0x0

#define HNS_ROCE_AEQ_DEFAULT_INTERVAL	0x0

#define HNS_ROCE_CEQ_DEFAULT_BURST_NUM	0x0

#define HNS_ROCE_CEQ_DEFAULT_INTERVAL	0x0



#define HNS_ROCE_V2_EQ_STATE_INVALID		0

#define HNS_ROCE_V2_EQ_STATE_VALID		1

#define HNS_ROCE_V2_EQ_STATE_OVERFLOW		2

#define HNS_ROCE_V2_EQ_STATE_FAILURE		3



#define HNS_ROCE_V2_EQ_OVER_IGNORE_0		0

#define HNS_ROCE_V2_EQ_OVER_IGNORE_1		1



#define HNS_ROCE_V2_EQ_COALESCE_0		0

#define HNS_ROCE_V2_EQ_COALESCE_1		1



#define HNS_ROCE_V2_EQ_FIRED			0

#define HNS_ROCE_V2_EQ_ARMED			1

#define HNS_ROCE_V2_EQ_ALWAYS_ARMED		3



#define HNS_ROCE_EQ_INIT_EQE_CNT		0

#define HNS_ROCE_EQ_INIT_PROD_IDX		0

#define HNS_ROCE_EQ_INIT_REPORT_TIMER		0

#define HNS_ROCE_EQ_INIT_MSI_IDX		0

#define HNS_ROCE_EQ_INIT_CONS_IDX		0

#define HNS_ROCE_EQ_INIT_NXT_EQE_BA		0



#define HNS_ROCE_V2_CEQ_CEQE_OWNER_S		31

#define HNS_ROCE_V2_AEQ_AEQE_OWNER_S		31



#define HNS_ROCE_V2_COMP_EQE_NUM		0x1000

#define HNS_ROCE_V2_ASYNC_EQE_NUM		0x1000



#define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S	0

#define HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S		1

#define HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S	2



#define HNS_ROCE_EQ_DB_CMD_AEQ			0x0

#define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED		0x1

#define HNS_ROCE_EQ_DB_CMD_CEQ			0x2

#define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED		0x3



#define EQ_ENABLE				1

#define EQ_DISABLE				0



#define EQ_REG_OFFSET				0x4



#define HNS_ROCE_INT_NAME_LEN			32

#define HNS_ROCE_V2_EQN_M GENMASK(23, 0)



#define HNS_ROCE_V2_CONS_IDX_M GENMASK(23, 0)



#define HNS_ROCE_V2_VF_ABN_INT_EN_S 0

#define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0)

#define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0)

#define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)

#define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)



/* WORD0 */

#define HNS_ROCE_EQC_EQ_ST_S 0

#define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0)



#define HNS_ROCE_EQC_HOP_NUM_S 2

#define HNS_ROCE_EQC_HOP_NUM_M GENMASK(3, 2)



#define HNS_ROCE_EQC_OVER_IGNORE_S 4

#define HNS_ROCE_EQC_OVER_IGNORE_M GENMASK(4, 4)



#define HNS_ROCE_EQC_COALESCE_S 5

#define HNS_ROCE_EQC_COALESCE_M GENMASK(5, 5)



#define HNS_ROCE_EQC_ARM_ST_S 6

#define HNS_ROCE_EQC_ARM_ST_M GENMASK(7, 6)



#define HNS_ROCE_EQC_EQN_S 8

#define HNS_ROCE_EQC_EQN_M GENMASK(15, 8)



#define HNS_ROCE_EQC_EQE_CNT_S 16

#define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16)



/* WORD1 */

#define HNS_ROCE_EQC_BA_PG_SZ_S 0

#define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0)



#define HNS_ROCE_EQC_BUF_PG_SZ_S 4

#define HNS_ROCE_EQC_BUF_PG_SZ_M GENMASK(7, 4)



#define HNS_ROCE_EQC_PROD_INDX_S 8

#define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8)



/* WORD2 */

#define HNS_ROCE_EQC_MAX_CNT_S 0

#define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0)



#define HNS_ROCE_EQC_PERIOD_S 16

#define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16)



/* WORD3 */

#define HNS_ROCE_EQC_REPORT_TIMER_S 0

#define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0)



/* WORD4 */

#define HNS_ROCE_EQC_EQE_BA_L_S 0

#define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0)



/* WORD5 */

#define HNS_ROCE_EQC_EQE_BA_H_S 0

#define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0)



/* WORD6 */

#define HNS_ROCE_EQC_SHIFT_S 0

#define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0)



#define HNS_ROCE_EQC_MSI_INDX_S 8

#define HNS_ROCE_EQC_MSI_INDX_M GENMASK(15, 8)



#define HNS_ROCE_EQC_CUR_EQE_BA_L_S 16

#define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16)



/* WORD7 */

#define HNS_ROCE_EQC_CUR_EQE_BA_M_S 0

#define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0)



/* WORD8 */

#define HNS_ROCE_EQC_CUR_EQE_BA_H_S 0

#define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0)



#define HNS_ROCE_EQC_CONS_INDX_S 8

#define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8)



/* WORD9 */

#define HNS_ROCE_EQC_NXT_EQE_BA_L_S 0

#define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0)



/* WORD10 */

#define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0

#define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0)



#define HNS_ROCE_V2_CEQE_COMP_CQN_S 0

#define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)



#define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0

#define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0)



#define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8

#define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8)



#define HNS_ROCE_V2_EQ_DB_CMD_S	16

#define HNS_ROCE_V2_EQ_DB_CMD_M	GENMASK(17, 16)



#define HNS_ROCE_V2_EQ_DB_TAG_S	0

#define HNS_ROCE_V2_EQ_DB_TAG_M	GENMASK(7, 0)



#define HNS_ROCE_V2_EQ_DB_PARA_S 0

#define HNS_ROCE_V2_EQ_DB_PARA_M GENMASK(23, 0)



#define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0

#define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0)



#endif
 
#endif