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Commit a4bdea86 authored by Shreyas K K's avatar Shreyas K K
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ARM: dts: msm: Add LLCC device nodes for Direwolf 

Add device nodes for Last level cache controller for
Direwolf target.

Change-Id: I7b207f8a63a9f466e5e3f1767b130137704fc73d
parent 282d9db0

bindings/arm/msm/qcom,llcc.txt

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ Properties: 
	            or "qcom,shima-llcc" or "qcom,sdxlemur-llcc"

	            or "qcom,yupik-llcc" or "qcom,sm8150-llcc"

		    or "qcom,sdmshrike-llcc" or "qcom,sm6150-llcc"

		    or "qcom,direwolf-llcc"

		    "qcom,llcc-v2" must be appended for V2 hardware.



- reg:

qcom/direwolf.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -1082,6 +1082,16 @@ 
		#mbox-cells = <1>;

	};



	cache-controller@9200000 {

		compatible = "qcom,direwolf-llcc", "qcom,llcc-v2";

		reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;

		reg-names = "llcc_base", "llcc_broadcast_base";

		cap-based-alloc-and-pwr-collapse;

		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&aopcc QDSS_CLK>;

		clock-names = "qdss_clk";

	};



	llcc_pmu: llcc-pmu@9095000 {

		compatible = "qcom,llcc-pmu-ver2";

		reg = <0x09095000 0x300>;