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Commit a4bada92 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add capacity and DPC properties for Blair"

parents 1ba9da53 2fde442f

qcom/blair.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -64,6 +64,8 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x0>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cpu-release-addr = <0x0 0x50000000>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {
@@ -83,6 +85,8 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x100>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cpu-release-addr = <0x0 0x50000000>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {
@@ -97,6 +101,8 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x200>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cpu-release-addr = <0x0 0x50000000>;

			next-level-cache = <&L2_2>;

			L2_2: l2-cache {
@@ -111,6 +117,8 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x300>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cpu-release-addr = <0x0 0x50000000>;

			next-level-cache = <&L2_3>;

			L2_3: l2-cache {
@@ -125,6 +133,8 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x400>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cpu-release-addr = <0x0 0x50000000>;

			next-level-cache = <&L2_4>;

			L2_4: l2-cache {
@@ -139,6 +149,8 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x500>;

			enable-method = "psci";

			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			cpu-release-addr = <0x0 0x50000000>;

			next-level-cache = <&L2_5>;

			L2_5: l2-cache {
@@ -153,6 +165,8 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x600>;

			enable-method = "psci";

			capacity-dmips-mhz = <1946>;

			dynamic-power-coefficient = <520>;

			cpu-release-addr = <0x0 0x50000000>;

			next-level-cache = <&L2_6>;

			L2_6: l2-cache {
@@ -167,6 +181,8 @@ 
			compatible = "qcom,kryo";

			reg = <0x0 0x700>;

			enable-method = "psci";

			capacity-dmips-mhz = <1946>;

			dynamic-power-coefficient = <520>;

			cpu-release-addr = <0x0 0x50000000>;

			next-level-cache = <&L2_7>;

			L2_7: l2-cache {