Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a4883ef6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull core irq changes from Ingo Molnar:
 "The main changes:

  - generic-irqchip driver additions, cleanups and fixes

  - 3 new irqchip drivers: ARMv7-M NVIC, TB10x and Marvell Orion SoCs

  - irq_get_trigger_type() simplification and cross-arch cleanup

  - various cleanups, simplifications

  - documentation updates"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (26 commits)
  softirq: Use _RET_IP_
  genirq: Add the generic chip to the genirq docbook
  genirq: generic-chip: Export some irq_gc_ functions
  genirq: Fix can_request_irq() for IRQs without an action
  irqchip: exynos-combiner: Staticize combiner_init
  irqchip: Add support for ARMv7-M NVIC
  irqchip: Add TB10x interrupt controller driver
  irqdomain: Use irq_get_trigger_type() to get IRQ flags
  MIPS: octeon: Use irq_get_trigger_type() to get IRQ flags
  arm: orion: Use irq_get_trigger_type() to get IRQ flags
  mfd: stmpe: use irq_get_trigger_type() to get IRQ flags
  mfd: twl4030-irq: Use irq_get_trigger_type() to get IRQ flags
  gpio: mvebu: Use irq_get_trigger_type() to get IRQ flags
  genirq: Add irq_get_trigger_type() to get IRQ flags
  genirq: Irqchip: document gcflags arg of irq_alloc_domain_generic_chips
  genirq: Set irq thread to RT priority on creation
  irqchip: Add support for Marvell Orion SoCs
  genirq: Add kerneldoc for irq_disable.
  genirq: irqchip: Add mask to block out invalid irqs
  genirq: Generic chip: Add linear irq domain support
  ...
parents ab3d681e d2e08473

Documentation/DocBook/genericirq.tmpl

+13 −0
Original line number Diff line number Diff line
@@ -464,6 +464,19 @@ if (desc->irq_data.chip->irq_eoi) 
	protected via desc->lock, by the generic layer.

     </para>

  </chapter>



  <chapter id="genericchip">

     <title>Generic interrupt chip</title>

     <para>

       To avoid copies of identical implementations of irq chips the

       core provides a configurable generic interrupt chip

       implementation. Developers should check carefuly whether the

       generic chip fits their needs before implementing the same

       functionality slightly different themself.

     </para>

!Ekernel/irq/generic-chip.c

  </chapter>



  <chapter id="structs">

     <title>Structures</title>

     <para>

Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt

0 → 100644
+38 −0
Original line number Diff line number Diff line 
TB10x Top Level Interrupt Controller

====================================



The Abilis TB10x SOC contains a custom interrupt controller. It performs

one-to-one mapping of external interrupt sources to CPU interrupts and

provides support for reconfigurable trigger modes.



Required properties

-------------------



- compatible: Should be "abilis,tb10x-ictl"

- reg: specifies physical base address and size of register range.

- interrupt-congroller: Identifies the node as an interrupt controller.

- #interrupt cells: Specifies the number of cells used to encode an interrupt

  source connected to this controller. The value shall be 2.

- interrupt-parent: Specifies the parent interrupt controller.

- interrupts: Specifies the list of interrupt lines which are handled by

  the interrupt controller in the parent controller's notation. Interrupts

  are mapped one-to-one to parent interrupts.



Example

-------



intc: interrupt-controller {	/* Parent interrupt controller */

	interrupt-controller;

	#interrupt-cells = <1>;	/* For example below */

	/* ... */

};



tb10x_ictl: pic@2000 {		/* TB10x interrupt controller */

	compatible = "abilis,tb10x-ictl";

	reg = <0x2000 0x20>;

	interrupt-controller;

	#interrupt-cells = <2>;

	interrupt-parent = <&intc>;

	interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

			20 21 22 23 24 25 26 27 28 29 30 31>;

};

Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt

0 → 100644
+48 −0
Original line number Diff line number Diff line 
Marvell Orion SoC interrupt controllers



* Main interrupt controller



Required properties:

- compatible: shall be "marvell,orion-intc"

- reg: base address(es) of interrupt registers starting with CAUSE register

- interrupt-controller: identifies the node as an interrupt controller

- #interrupt-cells: number of cells to encode an interrupt source, shall be 1



The interrupt sources map to the corresponding bits in the interrupt

registers, i.e.

- 0 maps to bit 0 of first base address,

- 1 maps to bit 1 of first base address,

- 32 maps to bit 0 of second base address, and so on.



Example:

	intc: interrupt-controller {

		compatible = "marvell,orion-intc";

		interrupt-controller;

		#interrupt-cells = <1>;

		 /* Dove has 64 first level interrupts */

		reg = <0x20200 0x10>, <0x20210 0x10>;

	};



* Bridge interrupt controller



Required properties:

- compatible: shall be "marvell,orion-bridge-intc"

- reg: base address of bridge interrupt registers starting with CAUSE register

- interrupts: bridge interrupt of the main interrupt controller

- interrupt-controller: identifies the node as an interrupt controller

- #interrupt-cells: number of cells to encode an interrupt source, shall be 1



Optional properties:

- marvell,#interrupts: number of interrupts provided by bridge interrupt

      controller, defaults to 32 if not set



Example:

	bridge_intc: interrupt-controller {

		compatible = "marvell,orion-bridge-intc";

		interrupt-controller;

		#interrupt-cells = <1>;

		reg = <0x20110 0x8>;

		interrupts = <0>;

		/* Dove bridge provides 5 interrupts */

		marvell,#interrupts = <5>;

	};

arch/arm/plat-orion/gpio.c

+1 −1
Original line number Diff line number Diff line
@@ -426,7 +426,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 
		if (!(cause & (1 << i)))

			continue;



		type = irqd_get_trigger_type(irq_get_irq_data(irq));

		type = irq_get_trigger_type(irq);

		if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {

			/* Swap polarity (race with GPIO line) */

			u32 polarity;

arch/mips/cavium-octeon/octeon-irq.c

+1 −1
Original line number Diff line number Diff line
@@ -607,7 +607,7 @@ static void octeon_irq_ciu_gpio_ack(struct irq_data *data) 


static void octeon_irq_handle_gpio(unsigned int irq, struct irq_desc *desc)

{

	if (irqd_get_trigger_type(irq_desc_get_irq_data(desc)) & IRQ_TYPE_EDGE_BOTH)

	if (irq_get_trigger_type(irq) & IRQ_TYPE_EDGE_BOTH)

		handle_edge_irq(irq, desc);

	else

		handle_level_irq(irq, desc);