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Commit a4751093 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'Add-comphy-support-for-Armada-38x' 



Russell King says:

====================
Add comphy support for Armada 38x

This series adds support for the comphy for Armada 38x, which allows
these SoCs to use 2500BASE-X mode with appropriate SFP modules.

Tested on SolidRun Clearfog after updating for the 5.0 merge window
changes.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents f06f095f f548ced1

Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ Optional properties: 
  "marvell,armada-370-neta" and 9800B for others.

- clock-names: List of names corresponding to clocks property; shall be

  "core" for core clock and "bus" for the optional bus clock.



- phys: comphy for the ethernet port, see ../phy/phy-bindings.txt



Optional properties (valid only for Armada XP/38x):

Documentation/devicetree/bindings/phy/phy-armada38x-comphy.txt

0 → 100644
+40 −0
Original line number Diff line number Diff line 
mvebu armada 38x comphy driver

------------------------------



This comphy controller can be found on Marvell Armada 38x. It provides a

number of shared PHYs used by various interfaces (network, sata, usb,

PCIe...).



Required properties:



- compatible: should be "marvell,armada-380-comphy"

- reg: should contain the comphy register location and length.

- #address-cells: should be 1.

- #size-cells: should be 0.



A sub-node is required for each comphy lane provided by the comphy.



Required properties (child nodes):



- reg: comphy lane number.

- #phy-cells : from the generic phy bindings, must be 1. Defines the

               input port to use for a given comphy lane.



Example:



	comphy: phy@18300 {

		compatible = "marvell,armada-380-comphy";

		reg = <0x18300 0x100>;

		#address-cells = <1>;

		#size-cells = <0>;



		cpm_comphy0: phy@0 {

			reg = <0>;

			#phy-cells = <1>;

		};



		cpm_comphy1: phy@1 {

			reg = <1>;

			#phy-cells = <1>;

		};

	};

arch/arm/boot/dts/armada-388-clearfog.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ 
	bm,pool-long = <2>;

	bm,pool-short = <1>;

	buffer-manager = <&bm>;

	phys = <&comphy1 1>;

	phy-mode = "sgmii";

	status = "okay";

};
@@ -103,6 +104,7 @@ 
	bm,pool-short = <1>;

	buffer-manager = <&bm>;

	managed = "in-band-status";

	phys = <&comphy5 2>;

	phy-mode = "sgmii";

	sfp = <&sfp>;

	status = "okay";

arch/arm/boot/dts/armada-38x.dtsi

+37 −0
Original line number Diff line number Diff line
@@ -335,6 +335,43 @@ 
				#clock-cells = <1>;

			};



			comphy: phy@18300 {

				compatible = "marvell,armada-380-comphy";

				reg = <0x18300 0x100>;

				#address-cells = <1>;

				#size-cells = <0>;



				comphy0: phy@0 {

					reg = <0>;

					#phy-cells = <1>;

				};



				comphy1: phy@1 {

					reg = <1>;

					#phy-cells = <1>;

				};



				comphy2: phy@2 {

					reg = <2>;

					#phy-cells = <1>;

				};



				comphy3: phy@3 {

					reg = <3>;

					#phy-cells = <1>;

				};



				comphy4: phy@4 {

					reg = <4>;

					#phy-cells = <1>;

				};



				comphy5: phy@5 {

					reg = <5>;

					#phy-cells = <1>;

				};

			};



			coreclk: mvebu-sar@18600 {

				compatible = "marvell,armada-380-core-clock";

				reg = <0x18600 0x04>;

drivers/net/ethernet/marvell/mvneta.c

+41 −4
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#include <linux/of_irq.h>

#include <linux/of_mdio.h>

#include <linux/of_net.h>

#include <linux/phy/phy.h>

#include <linux/phy.h>

#include <linux/phylink.h>

#include <linux/platform_device.h>
@@ -436,6 +437,7 @@ struct mvneta_port { 
	struct device_node *dn;

	unsigned int tx_csum_limit;

	struct phylink *phylink;

	struct phy *comphy;



	struct mvneta_bm *bm_priv;

	struct mvneta_bm_pool *pool_long;
@@ -3151,6 +3153,8 @@ static void mvneta_start_dev(struct mvneta_port *pp) 
{

	int cpu;



	WARN_ON(phy_power_on(pp->comphy));



	mvneta_max_rx_size_set(pp, pp->pkt_size);

	mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
@@ -3213,6 +3217,8 @@ static void mvneta_stop_dev(struct mvneta_port *pp) 


	mvneta_tx_reset(pp);

	mvneta_rx_reset(pp);



	WARN_ON(phy_power_off(pp->comphy));

}



static void mvneta_percpu_enable(void *arg)
@@ -3338,6 +3344,7 @@ static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 
static void mvneta_validate(struct net_device *ndev, unsigned long *supported,

			    struct phylink_link_state *state)

{

	struct mvneta_port *pp = netdev_priv(ndev);

	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };



	/* We only support QSGMII, SGMII, 802.3z and RGMII modes */
@@ -3358,8 +3365,13 @@ static void mvneta_validate(struct net_device *ndev, unsigned long *supported, 
	phylink_set(mask, Pause);



	/* Half-duplex at speeds higher than 100Mbit is unsupported */

	if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) {

		phylink_set(mask, 1000baseT_Full);

		phylink_set(mask, 1000baseX_Full);

	}

	if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) {

		phylink_set(mask, 2500baseX_Full);

	}



	if (!phy_interface_mode_is_8023z(state->interface)) {

		/* 10M and 100M are only supported in non-802.3z mode */
@@ -3373,6 +3385,11 @@ static void mvneta_validate(struct net_device *ndev, unsigned long *supported, 
		   __ETHTOOL_LINK_MODE_MASK_NBITS);

	bitmap_and(state->advertising, state->advertising, mask,

		   __ETHTOOL_LINK_MODE_MASK_NBITS);



	/* We can only operate at 2500BaseX or 1000BaseX.  If requested

	 * to advertise both, only report advertising at 2500BaseX.

	 */

	phylink_helper_basex_speed(state);

}



static int mvneta_mac_link_state(struct net_device *ndev,
@@ -3384,7 +3401,9 @@ static int mvneta_mac_link_state(struct net_device *ndev, 
	gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);



	if (gmac_stat & MVNETA_GMAC_SPEED_1000)

		state->speed = SPEED_1000;

		state->speed =

			state->interface == PHY_INTERFACE_MODE_2500BASEX ?

			SPEED_2500 : SPEED_1000;

	else if (gmac_stat & MVNETA_GMAC_SPEED_100)

		state->speed = SPEED_100;

	else
@@ -3499,12 +3518,20 @@ static void mvneta_mac_config(struct net_device *ndev, unsigned int mode, 
			    MVNETA_GMAC_FORCE_LINK_DOWN);

	}





	/* When at 2.5G, the link partner can send frames with shortened

	 * preambles.

	 */

	if (state->speed == SPEED_2500)

		new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;



	if (pp->comphy &&

	    (state->interface == PHY_INTERFACE_MODE_SGMII ||

	     state->interface == PHY_INTERFACE_MODE_1000BASEX ||

	     state->interface == PHY_INTERFACE_MODE_2500BASEX))

		WARN_ON(phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET,

					 state->interface));



	if (new_ctrl0 != gmac_ctrl0)

		mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);

	if (new_ctrl2 != gmac_ctrl2)
@@ -4404,7 +4431,7 @@ static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 
	if (phy_mode == PHY_INTERFACE_MODE_QSGMII)

		mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);

	else if (phy_mode == PHY_INTERFACE_MODE_SGMII ||

		 phy_mode == PHY_INTERFACE_MODE_1000BASEX)

		 phy_interface_mode_is_8023z(phy_mode))

		mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);

	else if (!phy_interface_mode_is_rgmii(phy_mode))

		return -EINVAL;
@@ -4421,6 +4448,7 @@ static int mvneta_probe(struct platform_device *pdev) 
	struct mvneta_port *pp;

	struct net_device *dev;

	struct phylink *phylink;

	struct phy *comphy;

	const char *dt_mac_addr;

	char hw_mac_addr[ETH_ALEN];

	const char *mac_from;
@@ -4446,6 +4474,14 @@ static int mvneta_probe(struct platform_device *pdev) 
		goto err_free_irq;

	}



	comphy = devm_of_phy_get(&pdev->dev, dn, NULL);

	if (comphy == ERR_PTR(-EPROBE_DEFER)) {

		err = -EPROBE_DEFER;

		goto err_free_irq;

	} else if (IS_ERR(comphy)) {

		comphy = NULL;

	}



	phylink = phylink_create(dev, pdev->dev.fwnode, phy_mode,

				 &mvneta_phylink_ops);

	if (IS_ERR(phylink)) {
@@ -4462,6 +4498,7 @@ static int mvneta_probe(struct platform_device *pdev) 
	pp = netdev_priv(dev);

	spin_lock_init(&pp->lock);

	pp->phylink = phylink;

	pp->comphy = comphy;

	pp->phy_interface = phy_mode;

	pp->dn = dn;