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Commit a33e1ece authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915/icl: Fix power well 2 wrt. DC-off toggling order 



To enable DC5/6 power well 2 has to be disabled as for previous
platforms, so fix things up.

Bspec: 4234
Fixes: 67ca07e7 ("drm/i915/icl: Add power well support")
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181102182200.17219-1-imre.deak@intel.com
parent 9a64c650

drivers/gpu/drm/i915/intel_runtime_pm.c

+6 −6
Original line number Original line Diff line number Diff line
@@ -2790,6 +2790,12 @@ static const struct i915_power_well_desc icl_power_wells[] = { 
			.hsw.has_fuses = true,

			.hsw.has_fuses = true,

		},

		},

	},

	},

	{

		.name = "DC off",

		.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,

		.ops = &gen9_dc_off_power_well_ops,

		.id = DISP_PW_ID_NONE,

	},

	{

	{

		.name = "power well 2",

		.name = "power well 2",

		.domains = ICL_PW_2_POWER_DOMAINS,

		.domains = ICL_PW_2_POWER_DOMAINS,
@@ -2801,12 +2807,6 @@ static const struct i915_power_well_desc icl_power_wells[] = { 
			.hsw.has_fuses = true,

			.hsw.has_fuses = true,

		},

		},

	},

	},

	{

		.name = "DC off",

		.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,

		.ops = &gen9_dc_off_power_well_ops,

		.id = DISP_PW_ID_NONE,

	},

	{

	{

		.name = "power well 3",

		.name = "power well 3",

		.domains = ICL_PW_3_POWER_DOMAINS,

		.domains = ICL_PW_3_POWER_DOMAINS,