Loading qcom/holi.dtsi +4 −4 Original line number Diff line number Diff line Loading @@ -2131,8 +2131,8 @@ sdhc_1: sdhci@4744000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x04744000 0x1000>, <0x04745000 0x1000>; reg-names = "hc_mem", "cqhci_mem"; reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>; reg-names = "hc_mem", "cqhci_mem", "cqhci_ice"; iommus = <&apps_smmu 0x20 0x0>; qcom,iommu-dma = "fastmap"; Loading Loading @@ -2509,8 +2509,8 @@ qcom_hwkm: hwkm@4440000 { compatible = "qcom,hwkm"; reg = <0x4440000 0x9000>, <0x04810000 0x9000>; reg-names = "km_master", "ice_slave"; reg = <0x4440000 0x9000>, <0x04810000 0x9000>, <0x04750000 0x9000>; reg-names = "km_master", "ice_slave", "sdcc_ice_slave"; qcom,enable-hwkm-clk; clock-names = "km_clk_src"; clocks = <&rpmcc RPM_SMD_HWKM_CLK>; Loading Loading
qcom/holi.dtsi +4 −4 Original line number Diff line number Diff line Loading @@ -2131,8 +2131,8 @@ sdhc_1: sdhci@4744000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x04744000 0x1000>, <0x04745000 0x1000>; reg-names = "hc_mem", "cqhci_mem"; reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>; reg-names = "hc_mem", "cqhci_mem", "cqhci_ice"; iommus = <&apps_smmu 0x20 0x0>; qcom,iommu-dma = "fastmap"; Loading Loading @@ -2509,8 +2509,8 @@ qcom_hwkm: hwkm@4440000 { compatible = "qcom,hwkm"; reg = <0x4440000 0x9000>, <0x04810000 0x9000>; reg-names = "km_master", "ice_slave"; reg = <0x4440000 0x9000>, <0x04810000 0x9000>, <0x04750000 0x9000>; reg-names = "km_master", "ice_slave", "sdcc_ice_slave"; qcom,enable-hwkm-clk; clock-names = "km_clk_src"; clocks = <&rpmcc RPM_SMD_HWKM_CLK>; Loading