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Commit a2b58537 authored by Avi Fishman's avatar Avi Fishman Committed by Daniel Lezcano
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clocksource/drivers/npcm: Fix GENMASK and timer operation 



NPCM7XX_Tx_OPER GENMASK bits are wrong, fix them.

Hopefully the NPCM7XX_REG_TICR0 register reset value of those bits was 0,
so it did not cause an issue.

The function npcm7xx_timer_oneshot() reads the register
NPCM7XX_REG_TCSR0, modifies it and then reads it again overwriting the
previous changes. Remove the extra read which is pointless.

The function npcm7xx_timer_periodic() is correct but the code writes
to the NPCM7XX_REG_TICR0 register while it is dealing with the
NPCM7XX_REG_TCSR0 register, that is confusing. Separate the write to
the registers in the code for the sake of clarity.

Fixes: 1c00289e ("clocksource/drivers/npcm: Add NPCM7xx timer driver")
Signed-off-by: default avatarAvi Fishman <avifishman70@gmail.com>
Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
parent 8d18f6fc

drivers/clocksource/timer-npcm7xx.c

+3 −6
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ 
#define NPCM7XX_Tx_INTEN		BIT(29)

#define NPCM7XX_Tx_COUNTEN		BIT(30)

#define NPCM7XX_Tx_ONESHOT		0x0

#define NPCM7XX_Tx_OPER			GENMASK(27, 3)

#define NPCM7XX_Tx_OPER			GENMASK(28, 27)

#define NPCM7XX_Tx_MIN_PRESCALE		0x1

#define NPCM7XX_Tx_TDR_MASK_BITS	24

#define NPCM7XX_Tx_MAX_CNT		0xFFFFFF
@@ -84,8 +84,6 @@ static int npcm7xx_timer_oneshot(struct clock_event_device *evt) 


	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);

	val &= ~NPCM7XX_Tx_OPER;



	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);

	val |= NPCM7XX_START_ONESHOT_Tx;

	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
@@ -97,12 +95,11 @@ static int npcm7xx_timer_periodic(struct clock_event_device *evt) 
	struct timer_of *to = to_timer_of(evt);

	u32 val;



	writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);



	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);

	val &= ~NPCM7XX_Tx_OPER;



	writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);

	val |= NPCM7XX_START_PERIODIC_Tx;



	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);



	return 0;